forked from koniifer/ableos
946 lines
23 KiB
Rust
946 lines
23 KiB
Rust
#![cfg_attr(
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not(any(target_arch = "x86_64", target_arch = "x86")),
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allow(dead_code)
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)]
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//! ```
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//! extern crate cupid;
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//!
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//! fn main() {
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//! let information = cupid::master();
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//! println!("{:#?}", information);
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//! if let Some(information) = information {
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//! if information.sse4_2() {
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//! println!("SSE 4.2 Available");
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//! }
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//! }
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//! }
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//! ```
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use core::arch::asm;
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use core::ops::Deref;
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use core::{fmt, slice, str};
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#[repr(u32)]
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pub enum RequestType {
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BasicInformation = 0x00000000,
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VersionInformation = 0x00000001,
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ThermalPowerManagementInformation = 0x00000006,
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StructuredExtendedInformation = 0x00000007,
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ExtendedFunctionInformation = 0x80000000,
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ExtendedProcessorSignature = 0x80000001,
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BrandString1 = 0x80000002,
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BrandString2 = 0x80000003,
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BrandString3 = 0x80000004,
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// reserved = 0x80000005,
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CacheLine = 0x80000006,
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TimeStampCounter = 0x80000007,
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PhysicalAddressSize = 0x80000008,
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}
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pub fn cpuid(code: RequestType) -> (u32, u32, u32, u32) {
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let eax;
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let ebx;
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let ecx;
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let edx;
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unsafe {
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asm!(
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"movq %rbx, {0:r}",
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"cpuid",
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"xchgq %rbx, {0:r}",
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lateout(reg) ebx,
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inlateout("eax") code as u32 => eax,
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inlateout("ecx") 0 => ecx,
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lateout("edx") edx,
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options(nostack, preserves_flags, att_syntax),
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);
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}
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(eax, ebx, ecx, edx)
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}
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/// The main entrypoint to the CPU information
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#[cfg(any(target_arch = "x86_64", target_arch = "x86"))]
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pub fn master() -> Option<Master> {
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Some(Master::new())
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}
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// This matches the Intel Architecture guide, with bits 31 -> 0.
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// The bit positions are inclusive.
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fn bits_of(val: u32, start_bit: u8, end_bit: u8) -> u32 {
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let mut silly = 0;
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for _ in start_bit..end_bit + 1 {
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silly <<= 1;
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silly |= 1;
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}
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(val >> start_bit) & silly
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}
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pub fn as_bytes(v: &u32) -> &[u8] {
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let start = v as *const u32 as *const u8;
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// TODO: use u32::BYTES
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unsafe { slice::from_raw_parts(start, 4) }
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}
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macro_rules! bit {
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($reg:ident, {$($idx:expr => $name:ident),+}) => {
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$(pub fn $name(self) -> bool {
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((self.$reg >> $idx) & 1) != 0
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})+
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}
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}
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macro_rules! dump {
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($me:expr, $f: expr, $sname:expr, {$($name:ident),+}) => {
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$f.debug_struct($sname)
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$(.field(stringify!($name), &$me.$name()))+
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.finish()
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}
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}
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macro_rules! delegate_flag {
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($item:ident, {$($name:ident),+}) => {
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$(pub fn $name(&self) -> bool {
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self.$item.map(|i| i.$name()).unwrap_or(false)
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})+
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}
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}
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macro_rules! master_attr_reader {
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($name:ident, $kind:ty) => {
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pub fn $name(&self) -> Option<&$kind> {
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self.$name.as_ref()
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}
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};
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}
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#[derive(Copy, Clone)]
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pub struct VersionInformation {
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eax: u32,
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ebx: u32,
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ecx: u32,
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edx: u32,
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}
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impl VersionInformation {
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pub fn new() -> VersionInformation {
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let (a, b, c, d) = cpuid(RequestType::VersionInformation);
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VersionInformation {
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eax: a,
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ebx: b,
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ecx: c,
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edx: d,
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}
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}
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pub fn family_id(self) -> u32 {
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let family_id = bits_of(self.eax, 8, 11);
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let extended_family_id = bits_of(self.eax, 20, 27);
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if family_id != 0x0F {
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family_id
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} else {
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extended_family_id + family_id
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}
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}
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pub fn model_id(self) -> u32 {
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let family_id = self.family_id();
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let model_id = bits_of(self.eax, 4, 7);
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let extended_model_id = bits_of(self.eax, 16, 19);
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if family_id == 0x06 || family_id == 0x0F {
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(extended_model_id << 4) + model_id
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} else {
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model_id
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}
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}
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pub fn stepping(self) -> u32 {
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bits_of(self.eax, 0, 3)
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}
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fn processor_signature(self) -> u32 {
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self.eax
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}
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pub fn brand_string(self) -> Option<&'static str> {
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let brand_index = bits_of(self.ebx, 0, 7);
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let processor_signature = self.processor_signature();
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match brand_index {
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0x00 => None,
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0x01 => Some("Intel(R) Celeron(R)"),
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0x02 => Some("Intel(R) Pentium(R) III"),
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0x03 => {
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if processor_signature == 0x06B1 {
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Some("Intel(R) Celeron(R)")
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} else {
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Some("Intel(R) Pentium(R) III Xeon(R)")
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}
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}
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0x04 => Some("Intel(R) Pentium(R) III"),
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0x06 => Some("Mobile Intel(R) Pentium(R) III-M"),
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0x07 => Some("Mobile Intel(R) Celeron(R)"),
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0x08 => Some("Intel(R) Pentium(R) 4"),
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0x09 => Some("Intel(R) Pentium(R) 4"),
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0x0A => Some("Intel(R) Celeron(R)"),
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0x0B => {
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if processor_signature == 0x0F13 {
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Some("Intel(R) Xeon(R) MP")
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} else {
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Some("Intel(R) Xeon(R)")
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}
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}
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0x0C => Some("Intel(R) Xeon(R) MP"),
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0x0E => {
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if processor_signature == 0x0F13 {
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Some("Intel(R) Xeon(R)")
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} else {
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Some("Mobile Intel(R) Pentium(R) 4-M")
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}
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}
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0x0F => Some("Mobile Intel(R) Celeron(R)"),
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0x11 => Some("Mobile Genuine Intel(R)"),
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0x12 => Some("Intel(R) Celeron(R) M"),
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0x13 => Some("Mobile Intel(R) Celeron(R)"),
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0x14 => Some("Intel(R) Celeron(R)"),
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0x15 => Some("Mobile Genuine Intel(R)"),
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0x16 => Some("Intel(R) Pentium(R) M"),
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0x17 => Some("Mobile Intel(R) Celeron(R)"),
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_ => None,
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}
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}
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bit!(ecx, {
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0 => sse3,
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1 => pclmulqdq,
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2 => dtes64,
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3 => monitor,
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4 => ds_cpl,
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5 => vmx,
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6 => smx,
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7 => eist,
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8 => tm2,
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9 => ssse3,
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10 => cnxt_id,
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11 => sdbg,
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12 => fma,
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13 => cmpxchg16b,
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14 => xtpr_update_control,
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15 => pdcm,
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// 16 - reserved
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17 => pcid,
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18 => dca,
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19 => sse4_1,
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20 => sse4_2,
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21 => x2apic,
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22 => movbe,
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23 => popcnt,
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24 => tsc_deadline,
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25 => aesni,
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26 => xsave,
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27 => osxsave,
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28 => avx,
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29 => f16c,
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30 => rdrand
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// 31 - unused
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});
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bit!(edx, {
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0 => fpu,
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1 => vme,
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2 => de,
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3 => pse,
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4 => tsc,
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5 => msr,
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6 => pae,
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7 => mce,
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8 => cx8,
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9 => apic,
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// 10 - reserved
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11 => sep,
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12 => mtrr,
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13 => pge,
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14 => mca,
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15 => cmov,
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16 => pat,
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17 => pse_36,
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18 => psn,
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19 => clfsh,
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// 20 - reserved
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21 => ds,
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22 => acpi,
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23 => mmx,
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24 => fxsr,
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25 => sse,
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26 => sse2,
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27 => ss,
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28 => htt,
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29 => tm,
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// 30 -reserved
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31 => pbe
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});
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}
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impl fmt::Debug for VersionInformation {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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dump!(self, f, "VersionInformation", {
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family_id,
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model_id,
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stepping,
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brand_string,
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sse3,
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pclmulqdq,
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dtes64,
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monitor,
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ds_cpl,
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vmx,
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smx,
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eist,
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tm2,
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ssse3,
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cnxt_id,
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sdbg,
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fma,
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cmpxchg16b,
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xtpr_update_control,
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pdcm,
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pcid,
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dca,
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sse4_1,
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sse4_2,
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x2apic,
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movbe,
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popcnt,
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tsc_deadline,
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aesni,
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xsave,
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osxsave,
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avx,
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f16c,
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rdrand,
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fpu,
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vme,
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de,
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pse,
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tsc,
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msr,
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pae,
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mce,
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cx8,
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apic,
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sep,
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mtrr,
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pge,
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mca,
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cmov,
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pat,
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pse_36,
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psn,
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clfsh,
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ds,
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acpi,
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mmx,
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fxsr,
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sse,
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sse2,
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ss,
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htt,
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tm,
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pbe
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})
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}
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}
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#[derive(Copy, Clone)]
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pub struct ExtendedProcessorSignature {
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ecx: u32,
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edx: u32,
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}
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impl ExtendedProcessorSignature {
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fn new() -> ExtendedProcessorSignature {
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let (_, _, c, d) = cpuid(RequestType::ExtendedProcessorSignature);
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ExtendedProcessorSignature { ecx: c, edx: d }
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}
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bit!(ecx, {
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0 => lahf_sahf_in_64_bit,
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// 1-4 reserved
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5 => lzcnt,
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// 6-7 reserved
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8 => prefetchw
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// 9-31 reserved
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});
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bit!(edx, {
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// 0-10 reserved
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11 => syscall_sysret_in_64_bit,
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// 12-19 reserved
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20 => execute_disable,
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// 21-25 reserved
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26 => gigabyte_pages,
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27 => rdtscp_and_ia32_tsc_aux,
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// 28 reserved
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29 => intel_64_bit_architecture
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// 30-31 reserved
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});
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}
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impl fmt::Debug for ExtendedProcessorSignature {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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dump!(self, f, "ThermalPowerManagementInformation", {
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lahf_sahf_in_64_bit,
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lzcnt,
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prefetchw,
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syscall_sysret_in_64_bit,
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execute_disable,
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gigabyte_pages,
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rdtscp_and_ia32_tsc_aux,
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intel_64_bit_architecture
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})
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}
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}
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// 3 calls of 4 registers of 4 bytes
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const BRAND_STRING_LENGTH: usize = 3 * 4 * 4;
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pub struct BrandString {
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bytes: [u8; BRAND_STRING_LENGTH],
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}
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impl BrandString {
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fn new() -> BrandString {
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fn append_bytes(a: RequestType, bytes: &mut [u8]) {
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let (a, b, c, d) = cpuid(a);
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let result_bytes = as_bytes(&a)
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.iter()
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.chain(as_bytes(&b).iter())
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.chain(as_bytes(&c).iter())
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.chain(as_bytes(&d).iter());
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for (output, input) in bytes.iter_mut().zip(result_bytes) {
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*output = *input
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}
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}
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let mut brand_string = BrandString {
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bytes: [0; BRAND_STRING_LENGTH],
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};
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append_bytes(RequestType::BrandString1, &mut brand_string.bytes[0..]);
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append_bytes(RequestType::BrandString2, &mut brand_string.bytes[16..]);
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append_bytes(RequestType::BrandString3, &mut brand_string.bytes[32..]);
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brand_string
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}
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}
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impl Clone for BrandString {
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fn clone(&self) -> Self {
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let mut bytes = [0; BRAND_STRING_LENGTH];
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for (d, s) in bytes.iter_mut().zip(self.bytes.iter()) {
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*d = *s;
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}
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BrandString { bytes: bytes }
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}
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}
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|
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impl Deref for BrandString {
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type Target = str;
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fn deref(&self) -> &str {
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let nul_terminator = self.bytes.iter().position(|&b| b == 0).unwrap_or(0);
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let usable_bytes = &self.bytes[..nul_terminator];
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unsafe { str::from_utf8_unchecked(usable_bytes) }.trim()
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}
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}
|
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|
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impl fmt::Display for BrandString {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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(self as &str).fmt(f)
|
|
}
|
|
}
|
|
|
|
impl fmt::Debug for BrandString {
|
|
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
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(self as &str).fmt(f)
|
|
}
|
|
}
|
|
|
|
#[derive(Copy, Clone)]
|
|
pub struct ThermalPowerManagementInformation {
|
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eax: u32,
|
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ebx: u32,
|
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ecx: u32,
|
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}
|
|
|
|
impl ThermalPowerManagementInformation {
|
|
fn new() -> ThermalPowerManagementInformation {
|
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let (a, b, c, _) = cpuid(RequestType::ThermalPowerManagementInformation);
|
|
ThermalPowerManagementInformation {
|
|
eax: a,
|
|
ebx: b,
|
|
ecx: c,
|
|
}
|
|
}
|
|
|
|
bit!(eax, {
|
|
0 => digital_temperature_sensor,
|
|
1 => intel_turbo_boost,
|
|
2 => arat,
|
|
// 3 - reserved
|
|
4 => pln,
|
|
5 => ecmd,
|
|
6 => ptm,
|
|
7 => hwp,
|
|
8 => hwp_notification,
|
|
9 => hwp_activity_window,
|
|
10 => hwp_energy_performance_preference,
|
|
// 12 - reserved
|
|
13 => hdc
|
|
});
|
|
|
|
pub fn number_of_interrupt_thresholds(self) -> u32 {
|
|
bits_of(self.ebx, 0, 3)
|
|
}
|
|
|
|
bit!(ecx, {
|
|
0 => hardware_coordination_feedback,
|
|
// 1-2 - reserved
|
|
3 => performance_energy_bias
|
|
});
|
|
}
|
|
|
|
impl fmt::Debug for ThermalPowerManagementInformation {
|
|
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
|
dump!(self, f, "ThermalPowerManagementInformation", {
|
|
digital_temperature_sensor,
|
|
intel_turbo_boost,
|
|
arat,
|
|
pln,
|
|
ecmd,
|
|
ptm,
|
|
hwp,
|
|
hwp_notification,
|
|
hwp_activity_window,
|
|
hwp_energy_performance_preference,
|
|
hdc,
|
|
|
|
number_of_interrupt_thresholds,
|
|
|
|
hardware_coordination_feedback,
|
|
performance_energy_bias
|
|
})
|
|
}
|
|
}
|
|
|
|
#[derive(Copy, Clone)]
|
|
pub struct StructuredExtendedInformation {
|
|
ebx: u32,
|
|
ecx: u32,
|
|
}
|
|
|
|
impl StructuredExtendedInformation {
|
|
fn new() -> StructuredExtendedInformation {
|
|
let (_, b, c, _) = cpuid(RequestType::StructuredExtendedInformation);
|
|
StructuredExtendedInformation { ebx: b, ecx: c }
|
|
}
|
|
|
|
bit!(ebx, {
|
|
0 => fsgsbase,
|
|
1 => ia32_tsc_adjust_msr,
|
|
// 2 - reserved
|
|
3 => bmi1,
|
|
4 => hle,
|
|
5 => avx2,
|
|
// 6 - reserved
|
|
7 => smep,
|
|
8 => bmi2,
|
|
9 => enhanced_rep_movsb_stosb,
|
|
10 => invpcid,
|
|
11 => rtm,
|
|
12 => pqm,
|
|
13 => deprecates_fpu_cs_ds,
|
|
// 14 - reserved
|
|
15 => pqe,
|
|
// 16-17 - reserved
|
|
18 => rdseed,
|
|
19 => adx,
|
|
20 => smap,
|
|
// 21-24 - reserved
|
|
25 => intel_processor_trace
|
|
// 26-31 - reserved
|
|
});
|
|
|
|
bit!(ecx, {
|
|
0 => prefetchwt1
|
|
});
|
|
}
|
|
|
|
impl fmt::Debug for StructuredExtendedInformation {
|
|
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
|
dump!(self, f, "StructuredExtendedInformation", {
|
|
fsgsbase,
|
|
ia32_tsc_adjust_msr,
|
|
bmi1,
|
|
hle,
|
|
avx2,
|
|
smep,
|
|
bmi2,
|
|
enhanced_rep_movsb_stosb,
|
|
invpcid,
|
|
rtm,
|
|
pqm,
|
|
deprecates_fpu_cs_ds,
|
|
pqe,
|
|
rdseed,
|
|
adx,
|
|
smap,
|
|
intel_processor_trace,
|
|
prefetchwt1
|
|
})
|
|
}
|
|
}
|
|
|
|
#[derive(Debug, Copy, Clone)]
|
|
pub enum CacheLineAssociativity {
|
|
Disabled,
|
|
DirectMapped,
|
|
TwoWay,
|
|
FourWay,
|
|
EightWay,
|
|
SixteenWay,
|
|
Full,
|
|
}
|
|
|
|
#[derive(Copy, Clone)]
|
|
pub struct CacheLine(u32);
|
|
|
|
impl CacheLine {
|
|
fn new() -> CacheLine {
|
|
let (_, _, c, _) = cpuid(RequestType::CacheLine);
|
|
CacheLine(c)
|
|
}
|
|
|
|
pub fn cache_line_size(self) -> u32 {
|
|
bits_of(self.0, 0, 7)
|
|
}
|
|
|
|
pub fn l2_associativity(self) -> Option<CacheLineAssociativity> {
|
|
match bits_of(self.0, 12, 15) {
|
|
0x00 => Some(CacheLineAssociativity::Disabled),
|
|
0x01 => Some(CacheLineAssociativity::DirectMapped),
|
|
0x02 => Some(CacheLineAssociativity::TwoWay),
|
|
0x04 => Some(CacheLineAssociativity::FourWay),
|
|
0x06 => Some(CacheLineAssociativity::EightWay),
|
|
0x08 => Some(CacheLineAssociativity::SixteenWay),
|
|
0x0F => Some(CacheLineAssociativity::Full),
|
|
_ => None,
|
|
}
|
|
}
|
|
|
|
pub fn cache_size(self) -> u32 {
|
|
bits_of(self.0, 16, 31)
|
|
}
|
|
}
|
|
|
|
impl fmt::Debug for CacheLine {
|
|
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
|
dump!(self, f, "CacheLine", {
|
|
cache_line_size,
|
|
l2_associativity,
|
|
cache_size
|
|
})
|
|
}
|
|
}
|
|
|
|
#[derive(Copy, Clone)]
|
|
pub struct TimeStampCounter {
|
|
edx: u32,
|
|
}
|
|
|
|
impl TimeStampCounter {
|
|
fn new() -> TimeStampCounter {
|
|
let (_, _, _, d) = cpuid(RequestType::TimeStampCounter);
|
|
TimeStampCounter { edx: d }
|
|
}
|
|
|
|
bit!(edx, {
|
|
// 0-7 - reserved
|
|
8 => invariant_tsc
|
|
// 9-31 - reserved
|
|
});
|
|
}
|
|
|
|
impl fmt::Debug for TimeStampCounter {
|
|
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
|
dump!(self, f, "TimeStampCounter", { invariant_tsc })
|
|
}
|
|
}
|
|
|
|
#[derive(Copy, Clone)]
|
|
pub struct PhysicalAddressSize(u32);
|
|
|
|
impl PhysicalAddressSize {
|
|
fn new() -> PhysicalAddressSize {
|
|
let (a, _, _, _) = cpuid(RequestType::PhysicalAddressSize);
|
|
PhysicalAddressSize(a)
|
|
}
|
|
|
|
pub fn physical_address_bits(self) -> u32 {
|
|
bits_of(self.0, 0, 7)
|
|
}
|
|
|
|
pub fn linear_address_bits(self) -> u32 {
|
|
bits_of(self.0, 8, 15)
|
|
}
|
|
}
|
|
|
|
impl fmt::Debug for PhysicalAddressSize {
|
|
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
|
dump!(self, f, "PhysicalAddressSize", {
|
|
physical_address_bits,
|
|
linear_address_bits
|
|
})
|
|
}
|
|
}
|
|
|
|
/// Information about the currently running processor
|
|
///
|
|
/// Feature flags match the feature mnemonic listed in the Intel
|
|
/// Instruction Set Reference. This struct provides a facade for flags
|
|
/// so the consumer doesn't need to worry about which particular CPUID
|
|
/// leaf provides the information.
|
|
///
|
|
/// For data beyond simple feature flags, you will need to retrieve
|
|
/// the nested struct and call the appropriate methods on it.
|
|
#[derive(Debug, Clone)]
|
|
pub struct Master {
|
|
// TODO: Rename struct
|
|
version_information: Option<VersionInformation>,
|
|
thermal_power_management_information: Option<ThermalPowerManagementInformation>,
|
|
structured_extended_information: Option<StructuredExtendedInformation>,
|
|
extended_processor_signature: Option<ExtendedProcessorSignature>,
|
|
brand_string: Option<BrandString>,
|
|
cache_line: Option<CacheLine>,
|
|
time_stamp_counter: Option<TimeStampCounter>,
|
|
physical_address_size: Option<PhysicalAddressSize>,
|
|
}
|
|
|
|
impl Master {
|
|
pub fn new() -> Master {
|
|
fn when_supported<F, T>(max: u32, kind: RequestType, then: F) -> Option<T>
|
|
where
|
|
F: FnOnce() -> T,
|
|
{
|
|
if max >= kind as u32 {
|
|
Some(then())
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
|
|
let (max_value, _, _, _) = cpuid(RequestType::BasicInformation);
|
|
|
|
let vi = when_supported(max_value, RequestType::VersionInformation, || {
|
|
VersionInformation::new()
|
|
});
|
|
let tpm = when_supported(
|
|
max_value,
|
|
RequestType::ThermalPowerManagementInformation,
|
|
|| ThermalPowerManagementInformation::new(),
|
|
);
|
|
let sei = when_supported(
|
|
max_value,
|
|
RequestType::StructuredExtendedInformation,
|
|
|| StructuredExtendedInformation::new(),
|
|
);
|
|
|
|
// Extended information
|
|
|
|
let (max_value, _, _, _) = cpuid(RequestType::ExtendedFunctionInformation);
|
|
|
|
let eps = when_supported(max_value, RequestType::ExtendedProcessorSignature, || {
|
|
ExtendedProcessorSignature::new()
|
|
});
|
|
let brand_string =
|
|
when_supported(max_value, RequestType::BrandString3, || BrandString::new());
|
|
let cache_line = when_supported(max_value, RequestType::CacheLine, || CacheLine::new());
|
|
let tsc = when_supported(max_value, RequestType::TimeStampCounter, || {
|
|
TimeStampCounter::new()
|
|
});
|
|
let pas = when_supported(max_value, RequestType::PhysicalAddressSize, || {
|
|
PhysicalAddressSize::new()
|
|
});
|
|
|
|
Master {
|
|
version_information: vi,
|
|
thermal_power_management_information: tpm,
|
|
structured_extended_information: sei,
|
|
extended_processor_signature: eps,
|
|
brand_string: brand_string,
|
|
cache_line: cache_line,
|
|
time_stamp_counter: tsc,
|
|
physical_address_size: pas,
|
|
}
|
|
}
|
|
|
|
master_attr_reader!(version_information, VersionInformation);
|
|
master_attr_reader!(
|
|
thermal_power_management_information,
|
|
ThermalPowerManagementInformation
|
|
);
|
|
master_attr_reader!(
|
|
structured_extended_information,
|
|
StructuredExtendedInformation
|
|
);
|
|
master_attr_reader!(extended_processor_signature, ExtendedProcessorSignature);
|
|
master_attr_reader!(cache_line, CacheLine);
|
|
master_attr_reader!(time_stamp_counter, TimeStampCounter);
|
|
master_attr_reader!(physical_address_size, PhysicalAddressSize);
|
|
|
|
pub fn brand_string(&self) -> Option<&str> {
|
|
self.brand_string
|
|
.as_ref()
|
|
.map(|bs| bs as &str)
|
|
.or(self.version_information.and_then(|vi| vi.brand_string()))
|
|
}
|
|
|
|
delegate_flag!(version_information, {
|
|
sse3,
|
|
pclmulqdq,
|
|
dtes64,
|
|
monitor,
|
|
ds_cpl,
|
|
vmx,
|
|
smx,
|
|
eist,
|
|
tm2,
|
|
ssse3,
|
|
cnxt_id,
|
|
sdbg,
|
|
fma,
|
|
cmpxchg16b,
|
|
xtpr_update_control,
|
|
pdcm,
|
|
pcid,
|
|
dca,
|
|
sse4_1,
|
|
sse4_2,
|
|
x2apic,
|
|
movbe,
|
|
popcnt,
|
|
tsc_deadline,
|
|
aesni,
|
|
xsave,
|
|
osxsave,
|
|
avx,
|
|
f16c,
|
|
rdrand,
|
|
fpu,
|
|
vme,
|
|
de,
|
|
pse,
|
|
tsc,
|
|
msr,
|
|
pae,
|
|
mce,
|
|
cx8,
|
|
apic,
|
|
sep,
|
|
mtrr,
|
|
pge,
|
|
mca,
|
|
cmov,
|
|
pat,
|
|
pse_36,
|
|
psn,
|
|
clfsh,
|
|
ds,
|
|
acpi,
|
|
mmx,
|
|
fxsr,
|
|
sse,
|
|
sse2,
|
|
ss,
|
|
htt,
|
|
tm,
|
|
pbe
|
|
});
|
|
|
|
delegate_flag!(thermal_power_management_information, {
|
|
digital_temperature_sensor,
|
|
intel_turbo_boost,
|
|
arat,
|
|
pln,
|
|
ecmd,
|
|
ptm,
|
|
hwp,
|
|
hwp_notification,
|
|
hwp_activity_window,
|
|
hwp_energy_performance_preference,
|
|
hdc,
|
|
hardware_coordination_feedback,
|
|
performance_energy_bias
|
|
});
|
|
|
|
delegate_flag!(structured_extended_information, {
|
|
fsgsbase,
|
|
ia32_tsc_adjust_msr,
|
|
bmi1,
|
|
hle,
|
|
avx2,
|
|
smep,
|
|
bmi2,
|
|
enhanced_rep_movsb_stosb,
|
|
invpcid,
|
|
rtm,
|
|
pqm,
|
|
deprecates_fpu_cs_ds,
|
|
pqe,
|
|
rdseed,
|
|
adx,
|
|
smap,
|
|
intel_processor_trace,
|
|
prefetchwt1
|
|
});
|
|
|
|
delegate_flag!(extended_processor_signature, {
|
|
lahf_sahf_in_64_bit,
|
|
lzcnt,
|
|
prefetchw,
|
|
syscall_sysret_in_64_bit,
|
|
execute_disable,
|
|
gigabyte_pages,
|
|
rdtscp_and_ia32_tsc_aux,
|
|
intel_64_bit_architecture
|
|
});
|
|
|
|
delegate_flag!(time_stamp_counter, { invariant_tsc });
|
|
}
|
|
/*
|
|
cfg_if! {
|
|
if #[cfg(any(target_arch = "x86_64", target_arch = "x86"))] {
|
|
|
|
#[test]
|
|
fn basic_genuine_intel() {
|
|
let (_, b, c, d) = cpuid(RequestType::BasicInformation);
|
|
|
|
assert_eq!(b"Genu", as_bytes(&b));
|
|
assert_eq!(b"ntel", as_bytes(&c));
|
|
assert_eq!(b"ineI", as_bytes(&d));
|
|
}
|
|
|
|
#[test]
|
|
fn brand_string_contains_intel() {
|
|
assert!(master().unwrap().brand_string().unwrap().contains("Intel(R)"))
|
|
}
|
|
|
|
} else {}
|
|
}
|
|
*/
|