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forked from AbleOS/ableos

Uuugh, jesus this sucks

This commit is contained in:
peony 2024-11-15 22:55:44 +01:00
parent b795aced8e
commit efcd6c0631

View file

@ -17,14 +17,16 @@ $NoDevice := DeviceID.(0xFFFF)
State := struct {value: u8}
$Recive := State.(0)
$Reboot := State.(1)
$GetID := State.(2)
$TurnOnStreaming := State.(3)
Port := struct {exists: bool, device: DeviceID, command_queued: bool, command_queue: u8, state: State, expecting: bool, expecting_data: u8}
Port := struct {exists: bool, device: DeviceID, commands_queued: u8, command_queue: [u8; 8], awaiting_ack: bool, state: State, expecting: bool, expecting_data: u8}
$check_bit := fn(value: u8, bit: u8, state: u8): bool {
return (value >> bit & 1) == state
}
ports := [Port].(.(true, NoDevice, false, 0xFF, Reboot, false, 0x0), .(true, NoDevice, false, 0xFF, Reboot, false, 0x0))
ports := [Port].(.(true, NoDevice, 1, .(0xFF, 0, 0, 0, 0, 0, 0, 0), false, Reboot, false, 0x0), .(true, NoDevice, 1, .(0xFF, 0, 0, 0, 0, 0, 0, 0), false, Reboot, false, 0x0))
initialize_controller := fn(): void {
memory.outb(0x64, 0xAD)
@ -67,13 +69,13 @@ initialize_controller := fn(): void {
log.info("Port 1 exists.\0")
memory.outb(0x64, 0xAE)
//Enables port 1.
ports[0].command_queued = true
ports[0].commands_queued = 1
}
if ports[1].exists {
log.info("Port 2 exists.\0")
memory.outb(0x64, 0xA8)
//Enables port 2.
ports[1].command_queued = true
ports[1].commands_queued = 1
}
}
@ -102,14 +104,14 @@ main := fn(): void {
}
if (port_info & 1) == 0 {
if ports[0].exists & ports[0].command_queued {
if ports[0].exists & ports[0].commands_queued > 0 {
memory.outb(0x60, ports[0].command_queue)
ports[0].command_queued = false
ports[0].commands_queued -= 1
}
if ports[1].exists & ports[1].command_queued {
if ports[1].exists & ports[1].commands_queued > 0 {
memory.outb(0x64, 0xD4)
memory.outb(0x60, ports[1].command_queue)
ports[1].command_queued = false
ports[1].commands_queued -= 1
}
}
@ -119,7 +121,12 @@ main := fn(): void {
}
if ports[port].exists {
@inline(handle_input, port, memory.inb(0x60))
input := memory.inb(0x60)
if ports[port].awaiting_ack & input == 0xFA {
ports[port].awaiting_ack = false
} else {
@inline(handle_input, port, input)
}
}
}
}