forked from AbleOS/holey-bytes
579 lines
25 KiB
Rust
579 lines
25 KiB
Rust
//! Welcome to the land of The Great Dispatch Loop
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//!
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//! Have fun
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use {
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super::{bmc::BlockCopier, mem::Memory, value::ValueVariant, Vm, VmRunError, VmRunOk},
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crate::{
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mem::{addr::AddressOp, Address},
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value::CheckedDivRem,
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},
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core::{cmp::Ordering, ops},
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hbbytecode::{
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OpsN, OpsO, OpsP, OpsRB, OpsRD, OpsRH, OpsRR, OpsRRA, OpsRRAH, OpsRRB, OpsRRD, OpsRRH,
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OpsRRO, OpsRROH, OpsRRP, OpsRRPH, OpsRRR, OpsRRRR, OpsRRW, OpsRW, RoundingMode,
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},
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};
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macro_rules! handler {
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($self:expr, |$ty:ident ($($ident:pat),* $(,)?)| $expr:expr) => {{
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#[allow(unused_unsafe)]
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let $ty($($ident),*) = unsafe { $self.decode::<$ty>() };
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#[allow(clippy::no_effect)] let e = $expr;
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$self.bump_pc::<$ty>();
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e
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}};
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}
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impl<Mem, const TIMER_QUOTIENT: usize> Vm<Mem, TIMER_QUOTIENT>
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where
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Mem: Memory,
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{
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/// Execute program
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///
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/// Program can return [`VmRunError`] if a trap handling failed
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#[cfg_attr(feature = "nightly", repr(align(4096)))]
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pub fn run(&mut self) -> Result<VmRunOk, VmRunError> {
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use hbbytecode::opcode::*;
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loop {
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// Big match
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//
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// Contribution guide:
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// - Zero register shall never be overwitten. It's value has to always be 0.
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// - Prefer `Self::read_reg` and `Self::write_reg` functions
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// - Try to use `handler!` macro for decoding and then bumping program counter
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// - Prioritise speed over code size
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// - Memory is cheap, CPUs not that much
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// - Do not heap allocate at any cost
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// - Yes, user-provided trap handler may allocate,
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// but that is not our »fault«.
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// - Unsafe is kinda must, but be sure you have validated everything
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// - Your contributions have to pass sanitizers, fuzzer and Miri
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// - Strictly follow the spec
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// - The spec does not specify how you perform actions, in what order,
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// just that the observable effects have to be performed in order and
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// correctly.
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// - Yes, we assume you run 64 bit CPU. Else ?conradluget a better CPU
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// sorry 8 bit fans, HBVM won't run on your Speccy :(
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unsafe {
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match self.memory.prog_read::<u8>(self.pc as _) {
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UN => {
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self.bump_pc::<OpsN>();
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return Err(VmRunError::Unreachable);
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}
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TX => {
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self.bump_pc::<OpsN>();
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return Ok(VmRunOk::End);
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}
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NOP => handler!(self, |OpsN()| ()),
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ADD8 => self.binary_op(u8::wrapping_add),
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ADD16 => self.binary_op(u16::wrapping_add),
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ADD32 => self.binary_op(u32::wrapping_add),
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ADD64 => self.binary_op(u64::wrapping_add),
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SUB8 => self.binary_op(u8::wrapping_sub),
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SUB16 => self.binary_op(u16::wrapping_sub),
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SUB32 => self.binary_op(u32::wrapping_sub),
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SUB64 => self.binary_op(u64::wrapping_sub),
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MUL8 => self.binary_op(u8::wrapping_mul),
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MUL16 => self.binary_op(u16::wrapping_mul),
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MUL32 => self.binary_op(u32::wrapping_mul),
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MUL64 => self.binary_op(u64::wrapping_mul),
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AND => self.binary_op::<u64>(ops::BitAnd::bitand),
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OR => self.binary_op::<u64>(ops::BitOr::bitor),
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XOR => self.binary_op::<u64>(ops::BitXor::bitxor),
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SLU8 => self.binary_op_shift::<u8>(u8::wrapping_shl),
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SLU16 => self.binary_op_shift::<u16>(u16::wrapping_shl),
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SLU32 => self.binary_op_shift::<u32>(u32::wrapping_shl),
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SLU64 => self.binary_op_shift::<u64>(u64::wrapping_shl),
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SRU8 => self.binary_op_shift::<u8>(u8::wrapping_shr),
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SRU16 => self.binary_op_shift::<u16>(u16::wrapping_shr),
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SRU32 => self.binary_op_shift::<u32>(u32::wrapping_shr),
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SRU64 => self.binary_op_shift::<u64>(u64::wrapping_shr),
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SRS8 => self.binary_op_shift::<i8>(i8::wrapping_shr),
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SRS16 => self.binary_op_shift::<i16>(i16::wrapping_shr),
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SRS32 => self.binary_op_shift::<i32>(i32::wrapping_shr),
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SRS64 => self.binary_op_shift::<i64>(i64::wrapping_shr),
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CMPU => handler!(self, |OpsRRR(tg, a0, a1)| self.cmp(
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tg,
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a0,
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self.read_reg(a1).cast::<u64>()
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)),
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CMPS => handler!(self, |OpsRRR(tg, a0, a1)| self.cmp(
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tg,
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a0,
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self.read_reg(a1).cast::<i64>()
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)),
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DIRU8 => self.dir::<u8>(),
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DIRU16 => self.dir::<u16>(),
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DIRU32 => self.dir::<u32>(),
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DIRU64 => self.dir::<u64>(),
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DIRS8 => self.dir::<i8>(),
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DIRS16 => self.dir::<i16>(),
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DIRS32 => self.dir::<i32>(),
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DIRS64 => self.dir::<i64>(),
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NEG => handler!(self, |OpsRR(tg, a0)| {
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// Bit negation
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self.write_reg(tg, !self.read_reg(a0).cast::<u64>())
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}),
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NOT => handler!(self, |OpsRR(tg, a0)| {
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// Logical negation
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self.write_reg(tg, u64::from(self.read_reg(a0).cast::<u64>() == 0));
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}),
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SXT8 => handler!(self, |OpsRR(tg, a0)| {
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self.write_reg(tg, self.read_reg(a0).cast::<i8>() as i64)
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}),
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SXT16 => handler!(self, |OpsRR(tg, a0)| {
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self.write_reg(tg, self.read_reg(a0).cast::<i16>() as i64)
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}),
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SXT32 => handler!(self, |OpsRR(tg, a0)| {
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self.write_reg(tg, self.read_reg(a0).cast::<i32>() as i64)
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}),
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ADDI8 => self.binary_op_imm(u8::wrapping_add),
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ADDI16 => self.binary_op_imm(u16::wrapping_add),
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ADDI32 => self.binary_op_imm(u32::wrapping_add),
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ADDI64 => self.binary_op_imm(u64::wrapping_add),
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MULI8 => self.binary_op_imm(u8::wrapping_mul),
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MULI16 => self.binary_op_imm(u16::wrapping_mul),
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MULI32 => self.binary_op_imm(u32::wrapping_mul),
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MULI64 => self.binary_op_imm(u64::wrapping_mul),
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ANDI => self.binary_op_imm::<u64>(ops::BitAnd::bitand),
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ORI => self.binary_op_imm::<u64>(ops::BitOr::bitor),
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XORI => self.binary_op_imm::<u64>(ops::BitXor::bitxor),
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SLUI8 => self.binary_op_ims::<u8>(u8::wrapping_shl),
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SLUI16 => self.binary_op_ims::<u16>(u16::wrapping_shl),
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SLUI32 => self.binary_op_ims::<u32>(u32::wrapping_shl),
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SLUI64 => self.binary_op_ims::<u64>(u64::wrapping_shl),
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SRUI8 => self.binary_op_ims::<u8>(u8::wrapping_shr),
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SRUI16 => self.binary_op_ims::<u16>(u16::wrapping_shr),
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SRUI32 => self.binary_op_ims::<u32>(u32::wrapping_shr),
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SRUI64 => self.binary_op_ims::<u64>(u64::wrapping_shr),
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SRSI8 => self.binary_op_ims::<i8>(i8::wrapping_shr),
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SRSI16 => self.binary_op_ims::<i16>(i16::wrapping_shr),
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SRSI32 => self.binary_op_ims::<i32>(i32::wrapping_shr),
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SRSI64 => self.binary_op_ims::<i64>(i64::wrapping_shr),
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CMPUI => handler!(self, |OpsRRD(tg, a0, imm)| { self.cmp(tg, a0, imm) }),
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CMPSI => handler!(self, |OpsRRD(tg, a0, imm)| { self.cmp(tg, a0, imm as i64) }),
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CP => handler!(self, |OpsRR(tg, a0)| self.write_reg(tg, self.read_reg(a0))),
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SWA => handler!(self, |OpsRR(r0, r1)| {
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// Swap registers
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match (r0, r1) {
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(0, 0) => (),
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(dst, 0) | (0, dst) => self.write_reg(dst, 0_u64),
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(r0, r1) => {
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core::ptr::swap(
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self.registers.get_unchecked_mut(usize::from(r0)),
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self.registers.get_unchecked_mut(usize::from(r1)),
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);
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}
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}
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}),
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LI8 => handler!(self, |OpsRB(tg, imm)| self.write_reg(tg, imm)),
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LI16 => handler!(self, |OpsRH(tg, imm)| self.write_reg(tg, imm)),
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LI32 => handler!(self, |OpsRW(tg, imm)| self.write_reg(tg, imm)),
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LI64 => handler!(self, |OpsRD(tg, imm)| self.write_reg(tg, imm)),
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LRA => handler!(self, |OpsRRO(tg, reg, off)| self.write_reg(
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tg,
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self.pcrel(off, 3)
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.wrapping_add(self.read_reg(reg).cast::<i64>())
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.get(),
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)),
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// Load. If loading more than register size, continue on adjecent registers
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LD => handler!(self, |OpsRRAH(dst, base, off, count)| self
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.load(dst, base, off, count)?),
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// Store. Same rules apply as to LD
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ST => handler!(self, |OpsRRAH(dst, base, off, count)| self
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.store(dst, base, off, count)?),
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LDR => handler!(self, |OpsRROH(dst, base, off, count)| self.load(
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dst,
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base,
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self.pcrel(off, 3).get(),
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count
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)?),
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STR => handler!(self, |OpsRROH(dst, base, off, count)| self.store(
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dst,
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base,
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self.pcrel(off, 3).get(),
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count
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)?),
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BMC => {
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// Block memory copy
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match if let Some(copier) = &mut self.copier {
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// There is some copier, poll.
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copier.poll(&mut self.memory)
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} else {
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// There is none, make one!
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let OpsRRH(src, dst, count) = self.decode();
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self.copier = Some(BlockCopier::new(
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Address::new(self.read_reg(src).cast()),
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Address::new(self.read_reg(dst).cast()),
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count as _,
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));
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self.copier
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.as_mut()
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.unwrap_unchecked() // SAFETY: We just assigned there
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.poll(&mut self.memory)
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} {
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// We are done, shift program counter
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core::task::Poll::Ready(Ok(())) => {
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self.copier = None;
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self.bump_pc::<OpsRRH>();
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}
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// Error, shift program counter (for consistency)
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// and yield error
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core::task::Poll::Ready(Err(e)) => {
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return Err(e.into());
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}
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// Not done yet, proceed to next cycle
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core::task::Poll::Pending => (),
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}
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}
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BRC => handler!(self, |OpsRRB(src, dst, count)| {
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// Block register copy
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if src.checked_add(count).is_none() || dst.checked_add(count).is_none() {
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return Err(VmRunError::RegOutOfBounds);
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}
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core::ptr::copy(
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self.registers.get_unchecked(usize::from(src)),
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self.registers.get_unchecked_mut(usize::from(dst)),
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usize::from(count),
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);
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}),
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JMP => {
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let OpsO(off) = self.decode();
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self.pc = self.pc.wrapping_add(off).wrapping_add(1);
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}
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JAL => {
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// Jump and link. Save PC after this instruction to
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// specified register and jump to reg + relative offset.
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let OpsRRO(save, reg, offset) = self.decode();
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self.write_reg(save, self.pc.get());
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self.pc = self
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.pcrel(offset, 3)
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.wrapping_add(self.read_reg(reg).cast::<i64>());
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}
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JALA => {
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// Jump and link. Save PC after this instruction to
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// specified register and jump to reg
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let OpsRRA(save, reg, offset) = self.decode();
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self.write_reg(save, self.pc.get());
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self.pc =
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Address::new(self.read_reg(reg).cast::<u64>().wrapping_add(offset));
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}
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// Conditional jumps, jump only to immediates
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JEQ => self.cond_jmp::<u64>(Ordering::Equal),
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JNE => {
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let OpsRRP(a0, a1, ja) = self.decode();
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if self.read_reg(a0).cast::<u64>() != self.read_reg(a1).cast::<u64>() {
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self.pc = self.pcrel(ja, 3);
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} else {
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self.bump_pc::<OpsRRP>();
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}
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}
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JLTS => self.cond_jmp::<u64>(Ordering::Less),
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JGTS => self.cond_jmp::<u64>(Ordering::Greater),
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JLTU => self.cond_jmp::<i64>(Ordering::Less),
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JGTU => self.cond_jmp::<i64>(Ordering::Greater),
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ECA => {
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// So we don't get timer interrupt after ECALL
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if TIMER_QUOTIENT != 0 {
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self.timer = self.timer.wrapping_add(1);
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}
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self.bump_pc::<OpsN>();
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return Ok(VmRunOk::Ecall);
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}
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EBP => {
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self.bump_pc::<OpsN>();
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return Ok(VmRunOk::Breakpoint);
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}
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FADD32 => self.binary_op::<f32>(ops::Add::add),
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FADD64 => self.binary_op::<f64>(ops::Add::add),
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FSUB32 => self.binary_op::<f32>(ops::Sub::sub),
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FSUB64 => self.binary_op::<f64>(ops::Sub::sub),
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FMUL32 => self.binary_op::<f32>(ops::Mul::mul),
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FMUL64 => self.binary_op::<f64>(ops::Mul::mul),
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FDIV32 => self.binary_op::<f32>(ops::Div::div),
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FDIV64 => self.binary_op::<f64>(ops::Div::div),
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FMA32 => self.fma::<f32>(),
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FMA64 => self.fma::<f64>(),
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FINV32 => handler!(self, |OpsRR(tg, reg)| self
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.write_reg(tg, 1. / self.read_reg(reg).cast::<f32>())),
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FINV64 => handler!(self, |OpsRR(tg, reg)| self
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.write_reg(tg, 1. / self.read_reg(reg).cast::<f64>())),
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FCMPLT32 => self.fcmp::<f32>(Ordering::Less),
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FCMPLT64 => self.fcmp::<f64>(Ordering::Less),
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FCMPGT32 => self.fcmp::<f32>(Ordering::Greater),
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FCMPGT64 => self.fcmp::<f64>(Ordering::Greater),
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ITF32 => handler!(self, |OpsRR(tg, reg)| self
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.write_reg(tg, self.read_reg(reg).cast::<i64>() as f32)),
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ITF64 => handler!(self, |OpsRR(tg, reg)| self
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.write_reg(tg, self.read_reg(reg).cast::<i64>() as f64)),
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FTI32 => handler!(self, |OpsRRB(tg, reg, mode)| self.write_reg(
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tg,
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crate::float::f32toint(
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self.read_reg(reg).cast::<f32>(),
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RoundingMode::try_from(mode)
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.map_err(|()| VmRunError::InvalidOperand)?,
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),
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)),
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FTI64 => handler!(self, |OpsRRB(tg, reg, mode)| self.write_reg(
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tg,
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crate::float::f64toint(
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self.read_reg(reg).cast::<f64>(),
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RoundingMode::try_from(mode)
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.map_err(|()| VmRunError::InvalidOperand)?,
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),
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)),
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FC32T64 => handler!(self, |OpsRR(tg, reg)| self
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.write_reg(tg, self.read_reg(reg).cast::<f32>() as f64)),
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FC64T32 => handler!(self, |OpsRRB(tg, reg, mode)| self.write_reg(
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tg,
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crate::float::conv64to32(
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self.read_reg(reg).cast(),
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RoundingMode::try_from(mode)
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.map_err(|()| VmRunError::InvalidOperand)?,
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),
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)),
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LRA16 => handler!(self, |OpsRRP(tg, reg, imm)| self.write_reg(
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tg,
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(self.pc + self.read_reg(reg).cast::<u64>() + imm + 3_u16).get(),
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)),
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LDR16 => handler!(self, |OpsRRPH(dst, base, off, count)| self.load(
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dst,
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base,
|
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self.pcrel(off, 3).get(),
|
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count
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)?),
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STR16 => handler!(self, |OpsRRPH(dst, base, off, count)| self.store(
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dst,
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base,
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self.pcrel(off, 3).get(),
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count
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)?),
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JMP16 => {
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let OpsP(off) = self.decode();
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self.pc = self.pcrel(off, 1);
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}
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op => return Err(VmRunError::InvalidOpcode(op)),
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}
|
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}
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|
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if TIMER_QUOTIENT != 0 {
|
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self.timer = self.timer.wrapping_add(1);
|
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if self.timer % TIMER_QUOTIENT == 0 {
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return Ok(VmRunOk::Timer);
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}
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}
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}
|
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}
|
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|
|
/// Bump instruction pointer
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|
#[inline(always)]
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fn bump_pc<T: Copy>(&mut self) {
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self.pc = self
|
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.pc
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.wrapping_add(core::mem::size_of::<T>())
|
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.wrapping_add(1);
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}
|
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|
|
/// Decode instruction operands
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|
#[inline(always)]
|
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unsafe fn decode<T: Copy>(&mut self) -> T {
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unsafe { self.memory.prog_read::<T>(self.pc + 1_u64) }
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}
|
|
|
|
/// Load
|
|
#[inline(always)]
|
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unsafe fn load(
|
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&mut self,
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dst: u8,
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base: u8,
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offset: u64,
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count: u16,
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) -> Result<(), VmRunError> {
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let n: u8 = match dst {
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0 => 1,
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_ => 0,
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};
|
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|
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unsafe {
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self.memory.load(
|
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self.ldst_addr_uber(dst, base, offset, count, n)?,
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|
self.registers
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.as_mut_ptr()
|
|
.add(usize::from(dst) + usize::from(n))
|
|
.cast(),
|
|
usize::from(count).saturating_sub(n.into()),
|
|
)
|
|
}?;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Store
|
|
#[inline(always)]
|
|
unsafe fn store(
|
|
&mut self,
|
|
dst: u8,
|
|
base: u8,
|
|
offset: u64,
|
|
count: u16,
|
|
) -> Result<(), VmRunError> {
|
|
unsafe {
|
|
self.memory.store(
|
|
self.ldst_addr_uber(dst, base, offset, count, 0)?,
|
|
self.registers.as_ptr().add(usize::from(dst)).cast(),
|
|
count.into(),
|
|
)
|
|
}?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Three-way comparsion
|
|
#[inline(always)]
|
|
unsafe fn cmp<T: ValueVariant + Ord>(&mut self, to: u8, reg: u8, val: T) {
|
|
self.write_reg(to, self.read_reg(reg).cast::<T>().cmp(&val) as i64);
|
|
}
|
|
|
|
/// Perform binary operating over two registers
|
|
#[inline(always)]
|
|
unsafe fn binary_op<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
|
let OpsRRR(tg, a0, a1) = unsafe { self.decode() };
|
|
self.write_reg(
|
|
tg,
|
|
op(self.read_reg(a0).cast::<T>(), self.read_reg(a1).cast::<T>()),
|
|
);
|
|
self.bump_pc::<OpsRRR>();
|
|
}
|
|
|
|
/// Perform binary operation over register and immediate
|
|
#[inline(always)]
|
|
unsafe fn binary_op_imm<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
|
|
#[derive(Clone, Copy)]
|
|
#[repr(packed)]
|
|
struct OpsRRImm<I>(OpsRR, I);
|
|
|
|
let OpsRRImm::<T>(OpsRR(tg, reg), imm) = unsafe { self.decode() };
|
|
self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
|
|
self.bump_pc::<OpsRRImm<T>>();
|
|
}
|
|
|
|
/// Perform binary operation over register and shift immediate
|
|
#[inline(always)]
|
|
unsafe fn binary_op_shift<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
|
|
let OpsRRR(tg, a0, a1) = unsafe { self.decode() };
|
|
self.write_reg(
|
|
tg,
|
|
op(
|
|
self.read_reg(a0).cast::<T>(),
|
|
self.read_reg(a1).cast::<u32>(),
|
|
),
|
|
);
|
|
self.bump_pc::<OpsRRR>();
|
|
}
|
|
|
|
/// Perform binary operation over register and shift immediate
|
|
#[inline(always)]
|
|
unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
|
|
let OpsRRB(tg, reg, imm) = unsafe { self.decode() };
|
|
self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm.into()));
|
|
self.bump_pc::<OpsRRW>();
|
|
}
|
|
|
|
/// Fused division-remainder
|
|
#[inline(always)]
|
|
unsafe fn dir<T: ValueVariant + CheckedDivRem>(&mut self) {
|
|
handler!(self, |OpsRRRR(td, tr, a0, a1)| {
|
|
let a0 = self.read_reg(a0).cast::<T>();
|
|
let a1 = self.read_reg(a1).cast::<T>();
|
|
|
|
if let Some(div) = a0.checked_div(a1) {
|
|
self.write_reg(td, div);
|
|
} else {
|
|
self.write_reg(td, -1_i64);
|
|
}
|
|
|
|
if let Some(rem) = a0.checked_rem(a1) {
|
|
self.write_reg(tr, rem);
|
|
} else {
|
|
self.write_reg(tr, a0);
|
|
}
|
|
});
|
|
}
|
|
|
|
/// Fused multiply-add
|
|
#[inline(always)]
|
|
unsafe fn fma<T>(&mut self)
|
|
where
|
|
T: ValueVariant + core::ops::Mul<Output = T> + core::ops::Add<Output = T>,
|
|
{
|
|
handler!(self, |OpsRRRR(tg, a0, a1, a2)| {
|
|
let a0 = self.read_reg(a0).cast::<T>();
|
|
let a1 = self.read_reg(a1).cast::<T>();
|
|
let a2 = self.read_reg(a2).cast::<T>();
|
|
self.write_reg(tg, a0 * a1 + a2)
|
|
});
|
|
}
|
|
|
|
/// Float comparsion
|
|
#[inline(always)]
|
|
unsafe fn fcmp<T: PartialOrd + ValueVariant>(&mut self, nan: Ordering) {
|
|
handler!(self, |OpsRRR(tg, a0, a1)| {
|
|
let a0 = self.read_reg(a0).cast::<T>();
|
|
let a1 = self.read_reg(a1).cast::<T>();
|
|
self.write_reg(tg, (a0.partial_cmp(&a1).unwrap_or(nan) as i8 + 1) as u8)
|
|
});
|
|
}
|
|
|
|
/// Calculate pc-relative address
|
|
#[inline(always)]
|
|
fn pcrel(&self, offset: impl AddressOp, pos: u8) -> Address {
|
|
self.pc.wrapping_add(pos).wrapping_add(offset)
|
|
}
|
|
|
|
/// Jump at `PC + #3` if ordering on `#0 <=> #1` is equal to expected
|
|
#[inline(always)]
|
|
unsafe fn cond_jmp<T: ValueVariant + Ord>(&mut self, expected: Ordering) {
|
|
let OpsRRP(a0, a1, ja) = unsafe { self.decode() };
|
|
if self
|
|
.read_reg(a0)
|
|
.cast::<T>()
|
|
.cmp(&self.read_reg(a1).cast::<T>())
|
|
== expected
|
|
{
|
|
self.pc = self.pcrel(ja, 3);
|
|
} else {
|
|
self.bump_pc::<OpsRRP>();
|
|
}
|
|
}
|
|
|
|
/// Load / Store Address check-computation überfunction
|
|
#[inline(always)]
|
|
unsafe fn ldst_addr_uber(
|
|
&self,
|
|
dst: u8,
|
|
base: u8,
|
|
offset: u64,
|
|
size: u16,
|
|
adder: u8,
|
|
) -> Result<Address, VmRunError> {
|
|
let reg = dst.checked_add(adder).ok_or(VmRunError::RegOutOfBounds)?;
|
|
|
|
if usize::from(reg) * 8 + usize::from(size) > 2048 {
|
|
Err(VmRunError::RegOutOfBounds)
|
|
} else {
|
|
self.read_reg(base)
|
|
.cast::<u64>()
|
|
.checked_add(offset)
|
|
.and_then(|x| x.checked_add(adder.into()))
|
|
.ok_or(VmRunError::AddrOutOfBounds)
|
|
.map(Address::new)
|
|
}
|
|
}
|
|
}
|