cleaning up some code
This commit is contained in:
parent
97eb985a02
commit
30bd6103a6
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@ -22,6 +22,7 @@ use {
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fmt::{self, Debug, Display, Write},
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fmt::{self, Debug, Display, Write},
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format_args as fa, mem,
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format_args as fa, mem,
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ops::{self, Deref},
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ops::{self, Deref},
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usize,
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},
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},
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hashbrown::hash_map,
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hashbrown::hash_map,
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hbbytecode::DisasmError,
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hbbytecode::DisasmError,
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@ -1051,14 +1052,15 @@ impl Nodes {
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&& self[target].inputs.len() == 4
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&& self[target].inputs.len() == 4
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&& self[value].kind != Kind::Load
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&& self[value].kind != Kind::Load
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&& self[store].kind == Kind::Stre
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&& self[store].kind == Kind::Stre
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&& self[store].lock_rc == 0
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&& self[store].inputs[2] == region
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&& self[store].inputs[2] == region
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{
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{
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if self[store].inputs[1] == value {
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if self[store].inputs[1] == value {
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return Some(store);
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return Some(store);
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}
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}
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return Some(self.modify_input(store, 1, value));
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let mut inps = self[target].inputs.clone();
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inps[3] = self[store].inputs[3];
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return Some(self.new_node_nop(self[target].ty, Kind::Stre, inps));
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}
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}
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}
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}
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K::Load => {
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K::Load => {
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@ -3163,7 +3165,9 @@ impl<'a> Codegen<'a> {
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self.ci.scope.aclasses.iter_mut().zip(scope.aclasses.iter_mut())
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self.ci.scope.aclasses.iter_mut().zip(scope.aclasses.iter_mut())
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{
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{
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if self.ci.nodes[scope_class.last_store.get()].is_lazy_phi(node) {
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if self.ci.nodes[scope_class.last_store.get()].is_lazy_phi(node) {
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if loop_class.last_store.get() != scope_class.last_store.get() {
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if loop_class.last_store.get() != scope_class.last_store.get()
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&& loop_class.last_store.get() != 0
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{
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scope_class.last_store.set(
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scope_class.last_store.set(
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self.ci.nodes.modify_input(
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self.ci.nodes.modify_input(
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scope_class.last_store.get(),
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scope_class.last_store.get(),
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@ -3237,7 +3241,9 @@ impl<'a> Codegen<'a> {
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.zip(bres.aclasses.iter_mut())
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.zip(bres.aclasses.iter_mut())
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{
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{
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if self.ci.nodes[scope_class.last_store.get()].is_lazy_phi(node) {
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if self.ci.nodes[scope_class.last_store.get()].is_lazy_phi(node) {
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if loop_class.last_store.get() != scope_class.last_store.get() {
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if loop_class.last_store.get() != scope_class.last_store.get()
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&& loop_class.last_store.get() != 0
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{
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scope_class.last_store.set(
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scope_class.last_store.set(
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self.ci.nodes.modify_input(
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self.ci.nodes.modify_input(
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scope_class.last_store.get(),
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scope_class.last_store.get(),
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@ -3300,11 +3306,6 @@ impl<'a> Codegen<'a> {
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}
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}
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}
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}
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let mut orig_classes = vec![];
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for (i, aclass) in self.ci.scope.aclasses.iter_mut().enumerate() {
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self.ci.nodes.load_loop_aclass(i, aclass, &mut self.ci.loops);
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orig_classes.push(aclass.dup(&mut self.ci.nodes));
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}
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let else_scope = self.ci.scope.dup(&mut self.ci.nodes);
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let else_scope = self.ci.scope.dup(&mut self.ci.nodes);
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self.ci.ctrl.set(
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self.ci.ctrl.set(
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@ -3324,8 +3325,6 @@ impl<'a> Codegen<'a> {
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self.ci.ctrl.get()
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self.ci.ctrl.get()
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};
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};
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orig_classes.into_iter().for_each(|c| c.remove(&mut self.ci.nodes));
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if lcntrl == Nid::MAX && rcntrl == Nid::MAX {
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if lcntrl == Nid::MAX && rcntrl == Nid::MAX {
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then_scope.clear(&mut self.ci.nodes);
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then_scope.clear(&mut self.ci.nodes);
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return None;
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return None;
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@ -2,31 +2,31 @@ main:
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ADDI64 r254, r254, -152d
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ADDI64 r254, r254, -152d
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LI8 r1, 0b
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LI8 r1, 0b
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LI8 r3, 1b
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LI8 r3, 1b
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ST r1, r254, 132a, 1h
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ST r1, r254, 116a, 1h
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ST r3, r254, 128a, 1h
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ST r3, r254, 112a, 1h
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ST r1, r254, 133a, 1h
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ST r1, r254, 117a, 1h
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ST r3, r254, 129a, 1h
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ST r3, r254, 113a, 1h
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ST r1, r254, 134a, 1h
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ST r1, r254, 118a, 1h
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ST r3, r254, 130a, 1h
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ST r3, r254, 114a, 1h
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ST r1, r254, 135a, 1h
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ST r1, r254, 119a, 1h
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ST r3, r254, 131a, 1h
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ST r3, r254, 115a, 1h
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LD r1, r254, 132a, 1h
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LD r1, r254, 116a, 1h
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LD r4, r254, 128a, 1h
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LD r4, r254, 112a, 1h
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ADD8 r5, r4, r1
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ADD8 r5, r4, r1
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LD r8, r254, 129a, 1h
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LD r8, r254, 113a, 1h
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LD r9, r254, 133a, 1h
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LD r9, r254, 117a, 1h
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ST r5, r254, 132a, 1h
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ST r5, r254, 116a, 1h
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ADD8 r12, r9, r8
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ADD8 r12, r9, r8
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LD r4, r254, 130a, 1h
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LD r4, r254, 114a, 1h
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LD r5, r254, 134a, 1h
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LD r5, r254, 118a, 1h
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ST r12, r254, 133a, 1h
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ST r12, r254, 117a, 1h
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ADD8 r7, r5, r4
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ADD8 r7, r5, r4
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ST r7, r254, 134a, 1h
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ST r7, r254, 118a, 1h
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ST r3, r254, 135a, 1h
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ST r3, r254, 119a, 1h
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LD r12, r254, 133a, 1h
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LD r12, r254, 117a, 1h
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LD r1, r254, 134a, 1h
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LD r1, r254, 118a, 1h
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ADD8 r4, r1, r12
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ADD8 r4, r1, r12
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LD r5, r254, 132a, 1h
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LD r5, r254, 116a, 1h
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ADD8 r7, r5, r4
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ADD8 r7, r5, r4
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LI8 r9, 4b
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LI8 r9, 4b
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ADD8 r1, r7, r3
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ADD8 r1, r7, r3
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@ -36,61 +36,61 @@ main:
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LI64 r1, 1008d
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LI64 r1, 1008d
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JMP :1
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JMP :1
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0: LI64 r6, 1d
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0: LI64 r6, 1d
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ADDI64 r5, r254, 80d
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ADDI64 r5, r254, 96d
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ST r6, r254, 80a, 8h
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ST r6, r254, 96a, 8h
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LI64 r9, 2d
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LI64 r9, 2d
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ST r9, r254, 88a, 8h
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ST r9, r254, 104a, 8h
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LI64 r2, 3d
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LI64 r2, 3d
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ADDI64 r1, r254, 64d
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ADDI64 r1, r254, 80d
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ST r2, r254, 48a, 8h
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ST r2, r254, 32a, 8h
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LI64 r6, 4d
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LI64 r6, 4d
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LI64 r2, 0d
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LI64 r2, 0d
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BMC r5, r1, 16h
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BMC r5, r1, 16h
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ST r6, r254, 56a, 8h
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ST r6, r254, 40a, 8h
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ST r2, r254, 0a, 8h
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ST r2, r254, 16a, 8h
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LD r11, r254, 64a, 8h
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LD r11, r254, 80a, 8h
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LD r1, r254, 48a, 8h
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LD r1, r254, 32a, 8h
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ST r2, r254, 8a, 8h
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ST r2, r254, 24a, 8h
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ADD64 r4, r1, r11
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ADD64 r4, r1, r11
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LD r7, r254, 72a, 8h
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LD r7, r254, 88a, 8h
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LD r2, r254, 0a, 8h
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LD r2, r254, 16a, 8h
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ST r4, r254, 96a, 8h
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ST r4, r254, 120a, 8h
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ADD64 r12, r7, r6
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ADD64 r12, r7, r6
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SUB64 r3, r2, r1
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SUB64 r3, r2, r1
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ADDI64 r8, r254, 16d
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ADDI64 r8, r254, 48d
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ST r12, r254, 104a, 8h
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ST r12, r254, 128a, 8h
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SUB64 r2, r1, r11
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SUB64 r2, r1, r11
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ST r3, r254, 16a, 8h
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ST r3, r254, 48a, 8h
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LI64 r9, -4d
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LI64 r9, -4d
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ST r2, r254, 112a, 8h
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ST r2, r254, 136a, 8h
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SUB64 r7, r6, r7
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SUB64 r7, r6, r7
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ST r9, r254, 24a, 8h
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ST r9, r254, 56a, 8h
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ADDI64 r8, r8, 16d
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ADDI64 r8, r8, 16d
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ST r7, r254, 120a, 8h
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ST r7, r254, 144a, 8h
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BMC r5, r8, 16h
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BMC r5, r8, 16h
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LD r6, r254, 96a, 8h
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LD r6, r254, 120a, 8h
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LD r8, r254, 16a, 8h
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LD r8, r254, 48a, 8h
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ADD64 r9, r8, r6
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ADD64 r9, r8, r6
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LD r11, r254, 24a, 8h
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LD r11, r254, 56a, 8h
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LD r1, r254, 104a, 8h
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LD r1, r254, 128a, 8h
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ST r9, r254, 16a, 8h
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ST r9, r254, 48a, 8h
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ADD64 r4, r1, r11
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ADD64 r4, r1, r11
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LD r8, r254, 32a, 8h
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LD r8, r254, 64a, 8h
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LD r9, r254, 112a, 8h
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LD r9, r254, 136a, 8h
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ST r4, r254, 24a, 8h
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ST r4, r254, 56a, 8h
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ADD64 r12, r9, r8
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ADD64 r12, r9, r8
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LD r2, r254, 40a, 8h
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LD r2, r254, 72a, 8h
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ST r12, r254, 32a, 8h
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ST r12, r254, 64a, 8h
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ADD64 r12, r2, r7
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ADD64 r12, r2, r7
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ST r12, r254, 40a, 8h
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ST r12, r254, 72a, 8h
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LD r7, r254, 16a, 8h
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LD r7, r254, 48a, 8h
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LD r9, r254, 32a, 8h
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LD r9, r254, 64a, 8h
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ADD64 r11, r9, r7
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ADD64 r11, r9, r7
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LD r1, r254, 24a, 8h
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LD r1, r254, 56a, 8h
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ST r11, r254, 136a, 8h
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ST r11, r254, 0a, 8h
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ADD64 r6, r1, r12
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ADD64 r6, r1, r12
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ST r6, r254, 144a, 8h
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ST r6, r254, 8a, 8h
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LD r7, r254, 136a, 8h
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LD r7, r254, 0a, 8h
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ADD64 r1, r7, r6
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ADD64 r1, r7, r6
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1: ADDI64 r254, r254, 152d
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1: ADDI64 r254, r254, 152d
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JALA r0, r31, 0a
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JALA r0, r31, 0a
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@ -1,26 +1,26 @@
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main:
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main:
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ADDI64 r254, r254, -10240d
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ADDI64 r254, r254, -10240d
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LI8 r6, 64b
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LI64 r6, 1d
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LI64 r7, 1d
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LI8 r7, 64b
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LI64 r8, 1024d
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LI64 r8, 1024d
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LI64 r9, 0d
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LI64 r9, 0d
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ADDI64 r5, r254, 0d
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ADDI64 r5, r254, 0d
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4: JLTU r9, r8, :0
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4: JLTU r9, r8, :0
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LI64 r4, 10d
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LI64 r4, 10d
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CP r6, r7
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CP r7, r6
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3: JLTU r6, r4, :1
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3: JLTU r7, r4, :1
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LD r10, r254, 2048a, 1h
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LD r10, r254, 2048a, 1h
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ANDI r1, r10, 255d
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ANDI r1, r10, 255d
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JMP :2
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JMP :2
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1: ADD64 r12, r6, r7
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1: ADD64 r12, r7, r6
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MULI64 r1, r6, 1024d
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MULI64 r1, r7, 1024d
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ADD64 r6, r5, r1
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ADD64 r7, r5, r1
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BMC r5, r6, 1024h
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BMC r5, r7, 1024h
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CP r6, r12
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CP r7, r12
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JMP :3
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JMP :3
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0: ADD64 r1, r9, r7
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0: ADD64 r1, r9, r6
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ADD64 r10, r5, r9
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ADD64 r10, r5, r9
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ST r6, r10, 0a, 1h
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ST r7, r10, 0a, 1h
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CP r9, r1
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CP r9, r1
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JMP :4
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JMP :4
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2: ADDI64 r254, r254, 10240d
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2: ADDI64 r254, r254, 10240d
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