506 lines
14 KiB
Markdown
506 lines
14 KiB
Markdown
# HoleyBytes ISA Specification
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# Bytecode format
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- Image format is not specified, though ELF is recommended
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- All numbers are encoded little-endian
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- There is 256 registers, they are represented by a byte
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- Immediate values are 8, 16, 32 or 64 bit
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## Instruction encoding
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- Instruction operands are packed (no alignment)
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- [opcode, operand 0, operand 1, …]
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## Instruction parameter types
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- `R`: Register (8 bytes)
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- Relative program-counter offset immediates:
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- `O`: 32 bit (Si32)
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- `P`: 16 bit (Si16)
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- Immediates:
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- `B`: Byte, 8 bit (Xi8)
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- `H`: Half-word, 16 bit (Xi16)
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- `W`: Word, 32 bit (Xi32)
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- `D`: Double-word, 64 bit (Xi64)
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- `A`: Absolute address immediate, 64 bit (Ui64)
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## Types
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- Si*n*: Signed integer of size *n* bits (Si8, Si16, Si32, Si64)
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- Ui*n*: Unsigned integer of size *n* bits (Ui8, Ui16, Ui32, Ui64)
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- Xi*n*: Sign-agnostic integer of size *n* bits (Xi8, Xi16, Xi32, Xi64)
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- Fl*n*: Floating point number of size *n* bits (Fl32, Fl64)
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# Behaviour
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- There is only one type of register, a general-purpose one.
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Used for both integers and floats.
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- Integer operations are wrapping, including signed numbers
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- Bitshifts are truncating
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- Two's complement
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- Floats as specified by IEEE 754
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- Execution model is implementation defined as long all observable
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effects are performed in correct order
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## Relative addressing
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Relative addresses are computed from address of the first byte
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of offset in the code. Not from the beginning of current or following instruction.
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## Zero register
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- Register 0
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- Cannot be clobbered
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- Write is no-op
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- Load always yields 0
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## Rounding modes
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| Rounding mode | Value |
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|:-------------------------|:------|
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| To nearest, ties to even | 0b00 |
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| Towards 0 (truncate) | 0b01 |
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| Towards +∞ (up) | 0b10 |
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| Towards -∞ (down) | 0b11 |
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- Remaining values in the byte traps with invalid operand exception
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# Memory
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- Memory implementation is implementation-defined
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- Zero address (`0x0`) is considered invalid
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# Traps
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- Environment call
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- Environment breakpoint
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Program counter goes to the following instruction
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## Exceptions
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- Memory access fault
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- Invalid operand
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- Unknown opcode
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Program counter stays on the currently executed instruction
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# Instructions
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- `#n`: register in parameter *n*
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- `$n`: for immediate in parameter *n*
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- `#P ← V`: Set register P to value V
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- `[x]`: Address x
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- `XY`: X bytes from location Y
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- `pc`: Program counter
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- `<XYZ>`: Placeholder
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- `Type(X)`: Cast
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## Program execution control
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- Type `N`
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| Opcode | Mnemonic | Action |
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|:-------|:---------|:--------------------------------------------|
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| 0x00 | UN | Throw unreachable code exception |
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| 0x01 | TX | Terminate execution (eg. on end of program) |
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| 0x02 | NOP | Do nothing |
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## Binary register-register ops
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- Type `RRR`
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- Action: `#0 ← #1 <OP> #2`
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## Addition (`+`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x03 | ADD8 | Xi8 |
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| 0x04 | ADD16 | Xi16 |
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| 0x05 | ADD32 | Xi32 |
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| 0x06 | ADD64 | Xi64 |
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## Subtraction (`-`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x07 | SUB8 | Xi8 |
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| 0x08 | SUB16 | Xi16 |
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| 0x09 | SUB32 | Xi32 |
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| 0x0A | SUB64 | Xi64 |
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## Multiplication (`*`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x0B | MUL8 | Xi8 |
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| 0x0C | MUL16 | Xi16 |
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| 0x0D | MUL32 | Xi32 |
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| 0x0E | MUL64 | Xi64 |
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## Bitwise ops (type: Xi64)
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| Opcode | Mnemonic | Operation |
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|:-------|:---------|:--------------------|
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| 0x0F | AND | Conjunction (&) |
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| 0x10 | OR | Disjunction (\|) |
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| 0x11 | XOR | Non-equivalence (^) |
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## Unsigned left bitshift (`<<`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x12 | SLU8 | Ui8 |
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| 0x13 | SLU16 | Ui16 |
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| 0x14 | SLU32 | Ui32 |
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| 0x15 | SLU64 | Ui64 |
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## Unsigned right bitshift (`>>`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x16 | SRU8 | Ui8 |
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| 0x17 | SRU16 | Ui16 |
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| 0x18 | SRU32 | Ui32 |
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| 0x19 | SRU64 | Ui64 |
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## Signed right bitshift (`>>`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x1A | SRS8 | Si8 |
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| 0x1B | SRS16 | Si16 |
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| 0x1C | SRS32 | Si32 |
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| 0x1D | SRS64 | Si64 |
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## Comparsion
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- Compares two numbers, saves result to register
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- Operation: `#0 ← #1 <=> #2`
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| Ordering | Number |
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|:---------|:-------|
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| < | -1 |
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| = | 0 |
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| > | 1 |
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x1E | CMPU | Ui64 |
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| 0x1F | CMPS | Si64 |
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# Merged divide-remainder
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- Type `RRRR`
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- Operation:
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- `#0 ← #2 / #3`
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- `#1 ← #2 % #3`
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- If dividing by zero:
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- `#0 ← Ui64(-1)`
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- `#1 ← #2`
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x20 | DIRU8 | Ui8 |
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| 0x21 | DIRU16 | Ui16 |
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| 0x22 | DIRU32 | Ui32 |
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| 0x23 | DIRU64 | Ui64 |
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| 0x24 | DIRS8 | Si8 |
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| 0x25 | DIRS16 | Si16 |
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| 0x26 | DIRS32 | Si32 |
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| 0x27 | DIRS64 | Si64 |
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# Unary register operations (type: Xi64)
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- Type: `RR`
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- Operation: `#0 ← <OP> #1`
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| Opcode | Mnemonic | Operation |
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|:-------|:---------|:-------------------------|
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| 0x28 | NEG | Bitwise complement (`~`) |
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| 0x29 | NOT | Logical negation (`!`) |
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## Sign extensions
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- Operation: `#0 ← Si64(#1)`
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| Opcode | Mnemonic | Source type |
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|:-------|:---------|:------------|
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| 0x2A | SXT8 | Si8 |
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| 0x2B | SXT16 | Si16 |
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| 0x2C | SXT32 | Si32 |
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# Binary register-immediate operations
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- Type: `RR<IMM>`
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- Operation: `#0 ← #1 <OP> $2`
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## Addition (`+`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x2D | ADDI8 | Xi8 |
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| 0x2E | ADDI16 | Xi16 |
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| 0x2F | ADDI32 | Xi32 |
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| 0x30 | ADDI64 | Xi64 |
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## Multiplication (`*`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x31 | MULI8 | Xi8 |
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| 0x32 | MULI16 | Xi16 |
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| 0x33 | MULI32 | Xi32 |
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| 0x34 | MULI64 | Xi64 |
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## Bitwise ops (type: Xi64)
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| Opcode | Mnemonic | Operation |
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|:-------|:---------|:--------------------|
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| 0x35 | ANDI | Conjunction (&) |
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| 0x36 | ORI | Disjunction (\|) |
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| 0x37 | XORI | Non-equivalence (^) |
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# Register-immediate bitshifts
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- Type: `RRB`
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- Operation: `#0 ← #1 <OP> $2`
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## Unsigned left bitshift (`<<`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x38 | SLUI8 | Ui8 |
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| 0x39 | SLUI16 | Ui16 |
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| 0x3A | SLUI32 | Ui32 |
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| 0x3B | SLUI64 | Ui64 |
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## Unsigned right bitshift (`>>`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x3C | SRUI8 | Ui8 |
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| 0x3D | SRUI16 | Ui16 |
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| 0x3E | SRUI32 | Ui32 |
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| 0x3F | SRUI64 | Ui64 |
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## Signed right bitshift (`>>`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x40 | SRSI8 | Si8 |
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| 0x41 | SRSI16 | Si16 |
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| 0x42 | SRSI32 | Si32 |
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| 0x43 | SRSI64 | Si64 |
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## Comparsion
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- Compares two numbers, saves result to register
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- Operation: `#0 ← #1 <=> $2`
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- Comparsion table same for register-register one
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x44 | CMPUI | Ui64 |
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| 0x45 | CMPSI | Si64 |
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# Register copies
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- Type: `RR`
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| Opcode | Mnemonic | Operation |
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|:-------|:---------|:---------------------------------|
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| 0x46 | CP | Copy register value (`#0 ← #1`) |
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| 0x47 | SWA | Swap register values (`#0 ⇆ #1`) |
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# Load immediate
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- Load immediate value from code to register
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- Type: `R<IMM>`
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- Operation: `#0 ← $1`
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x48 | LI8 | Xi8 |
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| 0x49 | LI16 | Xi16 |
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| 0x4A | Li32 | Xi32 |
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| 0x4B | Li64 | Xi64 |
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# Load relative address
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- Compute value from program counter, register value and offset
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- Type: `RRO`
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- Operation: `#0 ← pc + #1 + $2`
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| Opcode | Mnemonic |
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|:-------|:---------|
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| 0x4C | LRA |
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# Memory access operations
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- Immediate `$3` specifies size
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- If size is greater than register size,
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it overflows to adjecent register
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(eg. copying 16 bytes to register `r1` copies first 8 bytes to it
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and the remaining to `r2`)
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## Absolute addressing
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- Type: `RRAH`
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- Computes address from base register and absolute offset
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| Opcode | Mnemonic | Operation |
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|:-------|:---------|:-------------------|
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| 0x4D | LD | `#0 ← $3[#1 + $2]` |
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| 0x4E | ST | `$3[#1 + $2] ← #0` |
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## Relative addressing
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- Type: `RROH`
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- Computes address from register and offset from program counter
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| Opcode | Mnemonic | Operation |
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|:-------|:---------|:------------------------|
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| 0x4F | LDR | `#0 ← $3[pc + #1 + $2]` |
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| 0x50 | STR | `$3[pc + #1 + $2] ← #0` |
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# Block memory copy
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- Type: `RRH`
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- Copies block of `$3` bytes from memory location on address on `#0` to `#1`
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| Opcode | Mnemonic | Operation |
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|:-------|:---------|:------------------|
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| 0x51 | BMC | `$3[#1] ← $3[x0]` |
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# Block register copy
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- Type: `RRB`
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- Copy block of `$3` registers starting with `#0` to `#1`
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- Copying over the 256 registers causes an exception
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| Opcode | Mnemonic | Operation |
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|:-------|:---------|:--------------|
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| 0x52 | BRC | `$3#1 ← $3#0` |
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# Relative jump
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- Type: `O`
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| Opcode | Mnemonic | Operation |
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|:-------|:---------|:---------------|
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| 0x53 | JMP | `pc ← pc + $0` |
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# Linking jump
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- Operation:
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- Save address of following instruction to `#0`
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- `#0 ← pc+<instruction size>`
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- Jump to specified address
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| Opcode | Mnemonic | Instruction type | Address |
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|:-------|:---------|:------------------|:-------------------------|
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| 0x54 | JAL | RRO (size = 6 B) | Relative, `pc + #1 + $2` |
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| 0x55 | JALA | RRA (size = 10 B) | Absolute, `#1 + $2` |
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# Conditional jump
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- Perform comparsion, if operation met, jump to relative address
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- Type: `RRP`
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- Operation: `if #0 <CMP> #1 { pc ← pc + $2 }`
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| Opcode | Mnemonic | Condition | Type |
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|:-------|:---------|:-------------------|:-----|
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| 0x56 | JEQ | Equals (`=`) | Xi64 |
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| 0x57 | JNE | Not-equals (`≠`) | Xi64 |
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| 0x58 | JLTU | Less-than (`<`) | Ui64 |
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| 0x59 | JGTU | Greater-than (`>`) | Ui64 |
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| 0x5A | JLTS | Less-than (`<`) | Si64 |
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| 0x5B | JGTS | Greater-than (`>`) | Si64 |
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# Environment traps
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- Traps to the environment
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- Type: `N`
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| Opcode | Mnemonic | Trap type |
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|:-------|:---------|:-----------------|
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| 0x5C | ECA | Environment call |
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| 0x5D | EBP | Breakpoint |
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# Floating point binary operations
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- Type: `RRR`
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- Operation: `#0 ← #1 <OP> #2`
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| Opcode | Mnemonic | Operation | Type |
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|:-------|:---------|:---------------------|:-----|
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| 0x5E | FADD32 | Addition (`+`) | Fl32 |
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| 0x5F | FADD64 | Addition (`+`) | Fl64 |
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| 0x60 | FSUB32 | Subtraction (`-`) | Fl32 |
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| 0x61 | FSUB64 | Subtraction (`-`) | Fl64 |
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| 0x62 | FMUL32 | Multiplication (`*`) | Fl32 |
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| 0x63 | FMUL64 | Multiplication (`*`) | Fl64 |
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| 0x64 | FDIV32 | Division (`/`) | Fl32 |
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| 0x65 | FDIV64 | Division (`/`) | Fl64 |
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# Fused multiply-add
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- Type: `RRRR`
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- Operation: `#0 ← (#1 * #2) + #3`
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x66 | FMA32 | Fl32 |
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| 0x67 | FMA64 | Fl64 |
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# Comparsions
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- Type: `RRR`
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- Operation: `#0 ← #1 <=> #2`
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- Comparsion table same as for `CMPx`/`CMPxI`
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- NaN is less-than/greater-than depends on variant
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| Opcode | Mnemonic | Type | NaN is |
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|:-------|:---------|:-----|:-------|
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| 0x6A | FCMPLT32 | Fl32 | < |
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| 0x6B | FCMPLT64 | Fl64 | < |
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| 0x6C | FCMPGT32 | Fl32 | > |
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| 0x6D | FCMPGT64 | Fl64 | > |
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# Int to float
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- Type: `RR`
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- Converts from `Si64`
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- Operation: `#0 ← Fl<SIZE>(#1)`
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x6E | ITF32 | Fl32 |
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| 0x6F | ITF64 | Fl64 |
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# Float to int
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- Type: `RRB`
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- Operation: `#0 ← Si64(#1)`
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- Immediate `$2` specifies rounding mode
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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| 0x70 | FTI32 | Fl32 |
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| 0x71 | FTI64 | Fl64 |
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# Fl32 to Fl64
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- Type: `RR`
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- Operation: `#0 ← Fl64(#1)`
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| Opcode | Mnemonic |
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|:-------|:---------|
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| 0x72 | FC32T64 |
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# Fl64 to Fl32
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- Type: `RRB`
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- Operation: `#0 ← Fl32(#1)`
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- Immediate `$2` specified rounding mode
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| Opcode | Mnemonic |
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|:-------|:---------|
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| 0x73 | FC64T32 |
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# 16-bit relative address instruction variants
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| Opcode | Mnemonic | Type | Variant of |
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|:-------|:---------|:-----|:-----------|
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| 0x74 | LRA16 | RRP | LRA |
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| 0x75 | LDR16 | RRPH | LDR |
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| 0x76 | STR16 | RRPH | STR |
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| 0x77 | JMP16 | P | JMP |
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# psABI
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## C datatypes and alignment
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- One byte is 8 bits
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| C Type | Description | Byte sizes |
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|:------------|:-------------------------|:-----------|
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| char | Character / byte | 1 |
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| short | Short integer | 2 |
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| int | Integer | 4 |
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| long | Long integer | 8 |
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| long long | Long long integer | 8 |
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| float | Single-precision float | 4 |
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| double | Double-precision float | 8 |
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| long double | Extended-precision float | 8 |
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- Bikeshedding note: `long double` is now 8 bytes as
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the base ISA does not support `f128`. an extension
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for that should be made.
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## Call convention
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- Registers r1 – r31 are caller saved
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- Registers r32 – r255 are callee saved
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| Register | Description | Saver |
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|:-----------|:--------------------|:-------|
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| r0 | Hard-wired zero | N/A |
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| r1 - r2 | Return values | Caller |
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| r2 - r11 | Function parameters | Caller |
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| r12 - r30 | General purpose | Caller |
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| r31 | Return address | Caller |
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| r32 - r253 | General purpose | Callee |
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| r254 | Stack pointer | Callee |
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| r255 | Thread pointer | N/A |
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- If return value is too big to fit r1, r2 is also used.
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- Values larger than two double-words are passed by reference
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