272 lines
7.4 KiB
Markdown
272 lines
7.4 KiB
Markdown
# HoleyBytes ISA Specification
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# Bytecode format
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- All numbers are encoded little-endian
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- There is 256 registers, they are represented by a byte
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- Immediate values are 64 bit
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### Instruction encoding
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- Instruction parameters are packed (no alignment)
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- [opcode, …parameters…]
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### Instruction parameter types
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- B = Byte
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- D = Doubleword (64 bits)
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- H = Halfword (16 bits)
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| Name | Size |
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|:----:|:--------|
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| BBBB | 32 bits |
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| BBB | 24 bits |
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| BBDH | 96 bits |
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| BBDB | 88 bits |
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| BBD | 80 bits |
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| BB | 16 bits |
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| BD | 72 bits |
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| D | 64 bits |
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| N | 0 bits |
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# Instructions
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- `#n`: register in parameter *n*
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- `imm #n`: for immediate in parameter *n*
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- `P ← V`: Set register P to value V
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- `[x]`: Address x
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## No-op
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- N type
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| Opcode | Name | Action |
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|:------:|:----:|:----------:|
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| 0 | NOP | Do nothing |
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## Integer binary ops.
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- BBB type
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- `#0 ← #1 <op> #2`
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------:|
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| 1 | ADD | Wrapping addition |
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| 2 | SUB | Wrapping subtraction |
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| 3 | MUL | Wrapping multiplication |
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| 4 | AND | Bitand |
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| 5 | OR | Bitor |
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| 6 | XOR | Bitxor |
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| 7 | SL | Unsigned left bitshift |
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| 8 | SR | Unsigned right bitshift |
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| 9 | SRS | Signed right bitshift |
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### Comparsion
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| Opcode | Name | Action |
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|:------:|:----:|:-------------------:|
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| 10 | CMP | Signed comparsion |
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| 11 | CMPU | Unsigned comparsion |
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#### Comparsion table
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| #1 *op* #2 | Result |
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|:----------:|:------:|
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| < | -1 |
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| = | 0 |
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| > | 1 |
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### Division-remainder
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- Type BBBB
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- In case of `#3` is zero, the resulting value is all-ones
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- `#0 ← #2 ÷ #3`
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- `#1 ← #2 % #3`
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| Opcode | Name | Action |
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|:------:|:----:|:-------------------------------:|
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| 12 | DIR | Divide and remainder combinated |
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### Negations
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- Type BB
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- `#0 ← #1 <op> #2`
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| Opcode | Name | Action |
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|:------:|:----:|:----------------:|
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| 13 | NEG | Bit negation |
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| 14 | NOT | Logical negation |
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## Integer immediate binary ops.
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- Type BBD
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- `#0 ← #1 <op> imm #2`
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------:|
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| 15 | ADDI | Wrapping addition |
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| 16 | MULI | Wrapping subtraction |
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| 17 | ANDI | Bitand |
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| 18 | ORI | Bitor |
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| 19 | XORI | Bitxor |
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| 20 | SLI | Unsigned left bitshift |
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| 21 | SRI | Unsigned right bitshift |
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| 22 | SRSI | Signed right bitshift |
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### Comparsion
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- Comparsion is the same as when RRR type
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| Opcode | Name | Action |
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|:------:|:-----:|:-------------------:|
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| 23 | CMPI | Signed comparsion |
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| 24 | CMPUI | Unsigned comparsion |
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## Register value set / copy
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### Copy
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- Type BB
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- `#0 ← #1`
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| Opcode | Name | Action |
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|:------:|:----:|:------:|
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| 25 | CP | Copy |
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### Swap
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- Type BB
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- Swap #0 and #1
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| Opcode | Name | Action |
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|:------:|:----:|:------:|
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| 26 | SWA | Swap |
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### Load immediate
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- Type BD
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- `#0 ← #1`
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| Opcode | Name | Action |
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|:------:|:----:|:--------------:|
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| 27 | LI | Load immediate |
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## Memory operations
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- Type BBDH
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- If loaded/store value exceeds one register size, continue accessing following registers
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### Load / Store
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| Opcode | Name | Action |
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|:------:|:----:|:---------------------------------------:|
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| 28 | LD | `#0 ← [#1 + imm #3], copy imm #4 bytes` |
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| 29 | ST | `[#1 + imm #3] ← #0, copy imm #4 bytes` |
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## Block copy
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- Block copy source and target can overlap
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### Memory copy
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- Type BBD
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| Opcode | Name | Action |
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|:------:|:----:|:--------------------------------:|
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| 30 | BMC | `[#0] ← [#1], copy imm #2 bytes` |
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### Register copy
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- Type BBB
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- Copy a block a register to another location (again, overflowing to following registers)
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| Opcode | Name | Action |
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|:------:|:----:|:--------------------------------:|
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| 31 | BRC | `#0 ← #1, copy imm #2 registers` |
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## Control flow
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### Unconditional jump
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- Type BD
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| Opcode | Name | Action |
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|:------:|:----:|:---------------------:|
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| 32 | JMP | Jump at `#0 + imm #1` |
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### Conditional jumps
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- Type BBD
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- Jump at `imm #2` if `#0 <op> #1`
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| Opcode | Name | Comparsion |
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|:------:|:----:|:------------:|
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| 33 | JEQ | = |
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| 34 | JNE | ≠ |
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| 35 | JLT | < (signed) |
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| 36 | JGT | > (signed) |
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| 37 | JLTU | < (unsigned) |
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| 38 | JGTU | > (unsigned) |
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### Environment call
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- Type N
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| Opcode | Name | Action |
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|:------:|:-----:|:-------------------------------------:|
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| 39 | ECALL | Cause an trap to the host environment |
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## Floating point operations
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- Type BBB
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- `#0 ← #1 <op> #2`
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| Opcode | Name | Action |
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|:------:|:----:|:--------------:|
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| 40 | ADDF | Addition |
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| 41 | MULF | Multiplication |
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### Division-remainder
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- Type BBBB
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| Opcode | Name | Action |
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|:------:|:----:|:--------------------------------------:|
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| 42 | DIRF | Same flow applies as for integer `DIR` |
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## Floating point immediate operations
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- Type BBD
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- `#0 ← #1 <op> imm #2`
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| Opcode | Name | Action |
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|:------:|:-----:|:--------------:|
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| 43 | ADDFI | Addition |
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| 44 | MULFI | Multiplication |
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# Registers
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- There is 255 registers + one zero register (with index 0)
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- Reading from zero register yields zero
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- Writing to zero register is a no-op
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# Memory
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- Addresses are 64 bit
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- Memory implementation is arbitrary
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- In case of accessing invalid address:
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- Program shall trap (LoadAccessEx, StoreAccessEx) with parameter of accessed address
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- Value of register when trapped is undefined
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## Recommendations
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- Leave address `0x0` as invalid
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- If paging used:
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- Leave first page invalid
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- Pages should be at least 4 KiB
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# Program execution
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- The way of program execution is implementation defined
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- The order of instruction is arbitrary, as long all observable
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effects are applied in the program's order
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# Program validation
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- Invalid program should cause runtime error:
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- The form of error is arbitrary. Can be a trap or an interpreter-specified error
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- It shall not be handleable from within the program
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- Executing invalid opcode should trap
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- Program can be validaded either before execution or when executing
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# Traps
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Program should at least implement these traps:
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- Environment call
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- Invalid instruction exception
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- Load address exception
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- Store address exception
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and executing environment should be able to get information about them,
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like the opcode of invalid instruction or attempted address to load/store.
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Details about these are left as an implementation detail.
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# Assembly
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HoleyBytes assembly format is not defined, this is just a weak description
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of `hbasm` syntax.
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- Opcode names correspond to specified opcode names, lowercase (`nop`)
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- Parameters are separated by comma (`addi r0, r0, 1`)
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- Instructions are separated by either line feed or semicolon
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- Registers are represented by `r` followed by the number (`r10`)
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- Labels are defined by label name followed with colon (`loop:`)
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- Labels are references simply by their name (`print`)
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- Immediates are entered plainly. Negative numbers supported. |