forked from AbleOS/holey-bytes
242 lines
6.5 KiB
Markdown
242 lines
6.5 KiB
Markdown
# HoleyBytes ISA Specification
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# Bytecode format
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- All numbers are encoded little-endian
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- There is 60 registers (0 – 59), they are represented by a byte
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- Immediate values are 64 bit
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### Instruction encoding
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- Instruction parameters are packed (no alignment)
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- [opcode, …parameters…]
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### Instruction parameter types
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- R = Register
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- I = Immediate
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| Name | Size |
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|:----:|:--------|
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| RRRR | 32 bits |
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| RRR | 24 bits |
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| RRI | 80 bits |
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| RR | 16 bits |
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| RI | 72 bits |
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| I | 64 bits |
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| N | 0 bits |
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# Instructions
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- `#n`: register in parameter *n*
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- `imm #n`: for immediate in parameter *n*
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- `P ← V`: Set register P to value V
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- `[x]`: Address x
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## No-op
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- N type
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| Opcode | Name | Action |
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|:------:|:----:|:----------:|
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| 0 | NOP | Do nothing |
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## Integer binary ops.
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- RRR type
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- `#0 ← #1 <op> #2`
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------:|
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| 1 | ADD | Wrapping addition |
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| 2 | SUB | Wrapping subtraction |
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| 3 | MUL | Wrapping multiplication |
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| 4 | AND | Bitand |
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| 5 | OR | Bitor |
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| 6 | XOR | Bitxor |
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| 7 | SL | Unsigned left bitshift |
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| 8 | SR | Unsigned right bitshift |
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| 9 | SRS | Signed right bitshift |
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### Comparsion
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| Opcode | Name | Action |
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|:------:|:----:|:-------------------:|
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| 10 | CMP | Signed comparsion |
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| 11 | CMPU | Unsigned comparsion |
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#### Comparsion table
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| #1 *op* #2 | Result |
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|:----------:|:------:|
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| < | -1 |
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| = | 0 |
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| > | 1 |
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### Division-remainder
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- Type RRRR
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- In case of `#3` is zero, the resulting value is all-ones
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- `#0 ← #2 ÷ #3`
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- `#1 ← #2 % #3`
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| Opcode | Name | Action |
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|:------:|:----:|:-------------------------------:|
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| 12 | DIR | Divide and remainder combinated |
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### Negations
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- Type RR
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- `#0 ← #1 <op> #2`
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| Opcode | Name | Action |
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|:------:|:----:|:----------------:|
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| 13 | NEG | Bit negation |
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| 14 | NOT | Logical negation |
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## Integer immediate binary ops.
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- Type RRI
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- `#0 ← #1 <op> imm #2`
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------:|
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| 18 | ADDI | Wrapping addition |
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| 19 | MULI | Wrapping subtraction |
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| 20 | ANDI | Bitand |
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| 21 | ORI | Bitor |
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| 22 | XORI | Bitxor |
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| 23 | SLI | Unsigned left bitshift |
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| 24 | SRI | Unsigned right bitshift |
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| 25 | SRSI | Signed right bitshift |
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### Comparsion
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- Comparsion is the same as when RRR type
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| Opcode | Name | Action |
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|:------:|:-----:|:-------------------:|
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| 26 | CMPI | Signed comparsion |
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| 27 | CMPUI | Unsigned comparsion |
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## Register value set / copy
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### Copy
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- Type RR
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- `#0 ← #1`
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| Opcode | Name | Action |
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|:------:|:----:|:------:|
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| 28 | CP | Copy |
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### Load immediate
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- Type RI
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- `#0 ← #1`
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| Opcode | Name | Action |
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|:------:|:----:|:--------------:|
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| 29 | LI | Load immediate |
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## Memory operations
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- Type RRI
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### Load
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- `#0 ← [#1 + imm #2]`
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| Opcode | Name | Action |
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|:------:|:----:|:----------------------:|
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| 30 | LB | Load byte (8 bits) |
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| 31 | LD | Load doublet (16 bits) |
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| 32 | LQ | Load quadlet (32 bits) |
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| 33 | LO | Load octlet (64 bits) |
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### Store
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- `[#1 + imm #2] ← #0`
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------:|
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| 34 | SB | Store byte (8 bits) |
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| 35 | SD | Store doublet (16 bits) |
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| 36 | SQ | Store quadlet (32 bits) |
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| 37 | SO | Store octlet (64 bits) |
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## Control flow
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### Unconditional jump
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- Type RI
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| Opcode | Name | Action |
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|:------:|:----:|:---------------------:|
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| 38 | JMP | Jump at `#0 + imm #1` |
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### Conditional jumps
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- Type RRI
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- Jump at `imm #2` if `#0 <op> #1`
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| Opcode | Name | Comparsion |
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|:------:|:----:|:------------:|
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| 39 | JEQ | = |
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| 40 | JNE | ≠ |
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| 41 | JLT | < (signed) |
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| 42 | JGT | > (signed) |
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| 43 | JLTU | < (unsigned) |
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| 44 | JGTU | > (unsigned) |
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### Environment call
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- Type N
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| Opcode | Name | Action |
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|:------:|:-----:|:-------------------------------------:|
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| 45 | ECALL | Cause an trap to the host environment |
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## Floating point operations
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- Type RRR
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- `#0 ← #1 <op> #2`
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| Opcode | Name | Action |
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|:------:|:----:|:--------------:|
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| 46 | ADDF | Addition |
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| 47 | MULF | Multiplication |
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### Division-remainder
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- Type RRRR
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| Opcode | Name | Action |
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|:------:|:----:|:--------------------------------------:|
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| 48 | DIRF | Same flow applies as for integer `DIR` |
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## Floating point immediate operations
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- Type RRI
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- `#0 ← #1 <op> imm #2`
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| Opcode | Name | Action |
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|:------:|:-----:|:--------------:|
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| 49 | ADDFI | Addition |
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| 50 | MULFI | Multiplication |
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# Registers
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- There is 59 registers + one zero register (with index 0)
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- Reading from zero register yields zero
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- Writing to zero register is a no-op
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# Memory
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- Addresses are 64 bit
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- Memory implementation is arbitrary
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- In case of accessing invalid address:
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- Program shall trap (LoadAccessEx, StoreAccessEx) with parameter of accessed address
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- Value of register when trapped is undefined
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## Recommendations
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- Leave address `0x0` as invalid
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- If paging used:
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- Leave first page invalid
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- Pages should be at least 4 KiB
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# Program execution
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- The way of program execution is implementation defined
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- The order of instruction is arbitrary, as long all observable
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effects are applied in the program's order
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# Program validation
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- Invalid program should cause runtime error:
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- The form of error is arbitrary. Can be a trap or an interpreter-specified error
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- It shall not be handleable from within the program
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- Executing invalid opcode should trap
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- Program can be validaded either before execution or when executing
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# Traps
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| Name | Parameters | Cause |
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|:-------------:|:----------------:|:--------------------------:|
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| LoadAccessEx | Accessed address | Loading invalid address |
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| StoreAccessEx | Accessed address | Storing to invalid address |
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| InvalidOpcode | Loaded opcode | Executing invalid opcode |
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| Ecall | None | Ecall instruction |
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