134 lines
5.8 KiB
C
134 lines
5.8 KiB
C
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//
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// p5ctrnm.h
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//
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// Offset definition file for exensible counter objects and counters
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//
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// These "relative" offsets must start at 0 and be multiples of 2 (i.e.
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// even numbers). In the Open Procedure, they will be added to the
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// "First Counter" and "First Help" values fo the device they belong to,
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// in order to determine the absolute location of the counter and
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// object names and corresponding help text in the registry.
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//
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// this file is used by the extensible counter DLL code as well as the
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// counter name and help text definition file (.INI) file that is used
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// by LODCTR to load the names into the registry.
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//
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#define PENTIUM 0
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#define DATA_READ 2
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#define DATA_WRITE 4
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#define DATA_TLB_MISS 6
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#define DATA_READ_MISS 8
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#define DATA_WRITE_MISS 10
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#define WRITE_HIT_TO_ME_LINE 12
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#define DATA_CACHE_LINE_WB 14
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#define DATA_CACHE_SNOOPS 16
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#define DATA_CACHE_SNOOP_HITS 18
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#define MEMORY_ACCESSES_IN_PIPES 20
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#define BANK_CONFLICTS 22
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#define MISADLIGNED_DATA_REF 24
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#define CODE_READ 26
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#define CODE_TLB_MISS 28
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#define CODE_CACHE_MISS 30
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#define SEGMENT_LOADS 32
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#define BRANCHES 38
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#define BTB_HITS 40
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#define TAKEN_BRANCH_OR_BTB_HITS 42
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#define PIPELINE_FLUSHES 44
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#define INSTRUCTIONS_EXECUTED 46
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#define INSTRUCTIONS_EXECUTED_IN_VPIPE 48
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#define BUS_UTILIZATION 50
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#define PIPE_STALLED_ON_WRITES 52
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#define PIPE_STALLED_ON_READ 54
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#define STALLED_WHILE_EWBE 56
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#define LOCKED_BUS_CYCLE 58
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#define IO_RW_CYCLE 60
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#define NON_CACHED_MEMORY_REF 62
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#define PIPE_STALLED_ON_ADDR_GEN 64
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#define FLOPS 70
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#define DR0 72
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#define DR1 74
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#define DR2 76
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#define DR3 78
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#define INTERRUPTS 80
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#define DATA_RW 82
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#define DATA_RW_MISS 84
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#define PCT_DATA_READ_MISS 86
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#define PCT_DATA_WRITE_MISS 88
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#define PCT_DATA_RW_MISS 90
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#define PCT_DATA_TLB_MISS 92
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#define PCT_DATA_SNOOP_HITS 94
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#define PCT_CODE_READ_MISS 96
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#define PCT_CODE_TLB_MISS 98
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#define PCT_SEGMENT_CACHE_HITS 100
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#define PCT_BTB_HITS 102
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#define PCT_VPIPE_INST 104
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#define PCT_BRANCHES 106
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#define P6_LD_BLOCKS 108
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#define P6_SB_DRAINS 110
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#define P6_MISALIGN_MEM_REF 112
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#define P6_SEGMENT_REG_LOADS 114
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#define P6_FP_COMP_OPS_EXE 116
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#define P6_FP_ASSIST 118
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#define P6_MUL 120
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#define P6_DIV 122
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#define P6_CYCLES_DIV_BUSY 124
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#define P6_L2_ADS 126
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#define P6_L2_DBUS_BUSY 128
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#define P6_L2_DBUS_BUSY_RD 130
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#define P6_L2_LINES_IN 132
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#define P6_L2_M_LINES_IN 134
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#define P6_L2_LINES_OUT 136
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#define P6_L2_M_LINES_OUT 138
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#define P6_L2_IFETCH 140
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#define P6_L2_LD 142
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#define P6_L2_ST 144
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#define P6_L2_RQSTS 146
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#define P6_DATA_MEM_REFS 148
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#define P6_DCU_LINES_IN 150
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#define P6_DCU_M_LINES_IN 152
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#define P6_DCU_M_LINES_OUT 154
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#define P6_DCU_MISS_OUTSTANDING 156
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#define P6_BUS_REQ_OUTSTANDING 158
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#define P6_BUS_BNR_DRV 160
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#define P6_BUS_DRDY_CLOCKS 162
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#define P6_BUS_LOCK_CLOCKS 164
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#define P6_BUS_DATA_RCV 166
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#define P6_BUS_TRANS_BRD 168
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#define P6_BUS_TRANS_RFO 170
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#define P6_BUS_TRANS_WB 172
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#define P6_BUS_TRANS_IFETCH 174
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#define P6_BUS_TRANS_INVAL 176
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#define P6_BUS_TRANS_PWR 178
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#define P6_BUS_TRANS_P 180
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#define P6_BUS_TRANS_IO 182
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#define P6_BUS_TRANS_DEF 184
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#define P6_BUS_TRANS_BURST 186
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#define P6_BUS_TRANS_MEM 188
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#define P6_BUS_TRANS_ANY 190
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#define P6_CPU_CLK_UNHALTED 192
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#define P6_BUS_HIT_DRV 194
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#define P6_BUS_HITM_DRV 196
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#define P6_BUS_SNOOP_STALL 198
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#define P6_IFU_IFETCH 200
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#define P6_IFU_IFETCH_MISS 202
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#define P6_ITLB_MISS 204
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#define P6_IFU_MEM_STALL 206
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#define P6_ILD_STALL 208
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#define P6_RESOURCE_STALLS 210
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#define P6_INST_RETIRED 212
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#define P6_FLOPS 214
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#define P6_UOPS_RETIRED 216
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#define P6_BR_INST_RETIRED 218
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#define P6_BR_MISS_PRED_RETIRED 220
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#define P6_CYCLES_INT_MASKED 222
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#define P6_CYCLES_INT_PENDING_AND_MASKED 224
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#define P6_HW_INT_RX 226
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#define P6_BR_TAKEN_RETIRED 228
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#define P6_BR_MISS_PRED_TAKEN_RET 230
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#define P6_INST_DECODED 232
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#define P6_PARTIAL_RAT_STALLS 234
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#define P6_BR_INST_DECODED 236
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#define P6_BTB_MISSES 238
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#define P6_BR_BOGUS 240
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#define P6_BACLEARS 242
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