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LI16 and ADD16

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Bee 2023-11-15 18:58:20 -05:00
parent 7e855a03f4
commit 00eadf1b64
5 changed files with 49 additions and 6 deletions
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2
.gitignore vendored
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@ -1,5 +1,5 @@
impl/ impl/
**/*.gprj **/*.gprj*
tests/*.vcd tests/*.vcd
tests/out tests/out
src/gowin_*/ src/gowin_*/

8
src/beepo.v
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@ -1,4 +1,4 @@
`include "instructions.v" `include "instructions.v"
module Beepo #( module Beepo #(
parameter FREQ = 27_000_000, parameter FREQ = 27_000_000,
@ -89,8 +89,10 @@ module Beepo #(
`TX: r_arg_types_packed = `TX_ARGS; `TX: r_arg_types_packed = `TX_ARGS;
`NOP: r_arg_types_packed = `NOP_ARGS; `NOP: r_arg_types_packed = `NOP_ARGS;
`ADD8: r_arg_types_packed = `ADD8_ARGS; `ADD8: r_arg_types_packed = `ADD8_ARGS;
`ADD16: r_arg_types_packed = `ADD16_ARGS;
`ADDI8: r_arg_types_packed = `ADDI8_ARGS; `ADDI8: r_arg_types_packed = `ADDI8_ARGS;
`LI8: r_arg_types_packed = `LI8_ARGS; `LI8: r_arg_types_packed = `LI8_ARGS;
`LI16: r_arg_types_packed = `LI16_ARGS;
default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N}; default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N};
endcase endcase
@ -167,8 +169,10 @@ module Beepo #(
`TX: r_state <= DONE; `TX: r_state <= DONE;
`NOP: ; `NOP: ;
`ADD8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]); `ADD8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]);
`ADD16: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][15:0]);
`ADDI8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_arg_imm[7:0]); `ADDI8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_arg_imm[7:0]);
`LI8: set_register(r_arg_regs[0], r_arg_imm); `LI8: set_register(r_arg_regs[0], r_arg_imm);
`LI16: set_register(r_arg_regs[0], r_arg_imm);
endcase endcase
// r_tx_send_ctrl[0] <= ~r_tx_send_ctrl[0]; // r_tx_send_ctrl[0] <= ~r_tx_send_ctrl[0];
@ -201,7 +205,7 @@ module Beepo #(
Multi7 display ( Multi7 display (
.i_clk(i_clk), .i_clk(i_clk),
.i_hex({r_registers[1][7:0], r_registers[2][7:0]}), .i_hex({r_registers[1][15:0]}),
.o_segments_drive(o_segments_drive), .o_segments_drive(o_segments_drive),
.o_displays_neg(o_displays_neg) .o_displays_neg(o_displays_neg)
); );

4
src/instructions.v
View file

@ -11,6 +11,8 @@
// Binary register-register operations // Binary register-register operations
`define ADD8 'h03 `define ADD8 'h03
`define ADD8_ARGS {ARG_R, ARG_R, ARG_R, ARG_N} `define ADD8_ARGS {ARG_R, ARG_R, ARG_R, ARG_N}
`define ADD16 'h04
`define ADD16_ARGS {ARG_R, ARG_R, ARG_R, ARG_N}
// Merged divide-remainder // Merged divide-remainder
`define DIRU8 'h20 `define DIRU8 'h20
@ -32,6 +34,8 @@
// Load immediate // Load immediate
`define LI8 'h48 `define LI8 'h48
`define LI8_ARGS {ARG_R, ARG_B, ARG_N, ARG_N} `define LI8_ARGS {ARG_R, ARG_B, ARG_N, ARG_N}
`define LI16 'h49
`define LI16_ARGS {ARG_R, ARG_H, ARG_N, ARG_N}
// Conditional jump // Conditional jump
`define JEQ 'h56 `define JEQ 'h56

35
src/programs/add16.mi Normal file
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@ -0,0 +1,35 @@
#File_format=Bin
#Address_depth=32
#Data_width=8
00000000
01001001
00000001
00100011
01000110
01001001
00000010
01000110
00100011
00000011
00000001
00000001
00000010
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

6
tests/spmem.v
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@ -10,11 +10,11 @@ module spMem(
); );
reg [0:255] mem = { reg [0:255] mem = {
8'h0, 8'h0,
8'h48, 8'h01, 8'h23, 8'h49, 8'h01, 8'h23, 8'h46,
8'h48, 8'h02, 8'h46, 8'h49, 8'h02, 8'h46, 8'h23,
8'h03, 8'h01, 8'h01, 8'h02, 8'h03, 8'h01, 8'h01, 8'h02,
8'h01, 8'h01,
160'h0 144'h0
}; };
reg [7:0] r_out; reg [7:0] r_out;