what a mess
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parent
1727747fe5
commit
0794824fcd
5
.gitignore
vendored
5
.gitignore
vendored
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@ -3,4 +3,7 @@ impl/
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tests/**/*.vcd
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tests/**/out
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src/gowin_*/
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**/target/
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**/target/
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**/build/
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tests/slapper
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tests/hbasm
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@ -210,7 +210,7 @@ module Beepo #(
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.ce(1'b1), //input ce
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.reset(1'b0), //input reset
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.wre(1'b0), //input wre (write enable)
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.ad(r_pc_latch[31:0]), //input [15:0] ad
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.ad(r_pc_latch[0+:32]), //input [15:0] ad
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.din(1'b0) //input [7:0] din
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);
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endmodule
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@ -1,30 +0,0 @@
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ICARUS_FILES = inputs.txt
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# Used in all tests
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build:
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mkdir -p $@
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release/slapper:
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cargo build --manifest-path ../slapper/Cargo.toml -r
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slapper: release/slapper
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cp ../slapper/target/release/slapper $@
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# Addition tests
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build/adding: | build
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mkdir -p $@
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build/adding/program.bin: adding/program.rhai | build/adding
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./hbasm $< > $@
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build/adding/spmem_gen.v: build/adding/program.bin slapper | build/adding
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./slapper $< spmem.v $@
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build/adding/out: ${ICARUS_FILES} build/adding/spmem_gen.v | build/adding
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iverilog -o $@ -c $< -s tb_adding
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build/adding/dump.vcd: build/adding/out | build/adding
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vvp $<
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adding-wave: build/adding/dump.vcd | build/adding
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gtkwave build/adding/dump.vcd
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38
tests/adding/Makefile
Normal file
38
tests/adding/Makefile
Normal file
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@ -0,0 +1,38 @@
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SLAPPER_DIR = ../../slapper
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SLAPPER_BUILD = ${SLAPPER_DIR}/target/release/slapper
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SLAPPER = ../slapper
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HBASM = ../hbasm
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SPMEM = ../spmem.v
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INPUT_FILE = inputs.txt
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BUILD_DEPS = ../../src/beepo.v ../../src/instructions.v adding.v ../../src/uart_tx.v ../../src/multi7.v build/spmem_gen.v
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${SLAPPER_BUILD}:
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cargo build --manifest-path ${SLAPPER_DIR}/Cargo.toml -r
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${SLAPPER}: ${SLAPPER_BUILD}
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cp $< $@
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build:
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mkdir -p $@
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build/program.bin: program.rhai | build
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${HBASM} $< > $@
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build/spmem_gen.v: build/program.bin ${SLAPPER}
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${SLAPPER} $< ${SPMEM} $@
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build/out: ${INPUT_FILE} ${BUILD_DEPS} build/spmem_gen.v
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iverilog -o $@ -c $< -s tb_adding
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build/dump.vcd: build/out
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vvp $<
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wave: build/dump.vcd
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gtkwave build/dump.vcd
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assemble: build/program.bin
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insert-mem: build/spmem_gen.v
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synthesize: build/out
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run: build/dump.vcd
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@ -1 +0,0 @@
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HIJK-./0
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@ -21,19 +21,14 @@ module tb_adding();
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always #(CLK_PERIOD/2) clk=~clk;
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars(0, tb_adding,
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bep.r_registers[1], bep.r_registers[2],
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bep.r_arg_types[0], bep.r_arg_types[1],
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bep.r_arg_types[2], bep.r_arg_types[3],
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bep.r_arg_regs[0], bep.r_arg_regs[1],
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bep.r_arg_regs[2], bep.r_arg_regs[3]
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);
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$dumpfile("build/dump.vcd");
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$dumpvars(0, tb_adding, bep.r_registers[1]);
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end
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// should probably do more granular tests
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initial #10000 begin
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`assert(bep.r_registers[1], 64'h2020202040406090);
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$display("[ADDING] All tests passed");
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$finish;
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end
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endmodule
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@ -1 +0,0 @@
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HIJK-./0
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@ -1,24 +0,0 @@
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module spMem(
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output [7:0] dout,
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input clk,
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input oce,
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input ce,
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input reset,
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input wre,
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input [15:0] ad,
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input [7:0] din
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);
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// gets replaced with the memory for the program to run
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reg [0:535] mem = 536'h480110490210104A03101010104B041010101010101010030101010401010205010103060101042D0101102E010110102F010110101010300101101010101010101001;
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reg [15:0] r_ad_prev = 0;
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reg [7:0] r_out;
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assign dout = r_out;
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always @(negedge clk) begin
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// one full clock cycle before being fetched
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if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
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else r_ad_prev = ad;
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end
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endmodule
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@ -2,4 +2,4 @@
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adding.v
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../../src/uart_tx.v
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../../src/multi7.v
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../build/adding_mem.v
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build/spmem_gen.v
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@ -1,7 +0,0 @@
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with open("adding.bin", "rb") as f:
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content = f.read()
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length_bits = len(content) * 8
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mash = "".join([hex(int(i))[2:].zfill(2) for i in content])
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shadow = f"reg [0:{length_bits-1}] mem = {length_bits}'h{mash}; // generated"
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print(shadow)
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