34 lines
747 B
Verilog
34 lines
747 B
Verilog
`include "../../src/beepo.v"
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`timescale 100us/10ns
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`define assert(signal, value) \
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if (signal !== value) begin \
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$display("ASSERTION FAILED in %m: signal != value"); \
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$finish; \
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end
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module tb_adding();
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reg clk = 0;
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Beepo #(
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.FREQ(1),
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.UART_BAUD(1_000_000)
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) bep (
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.i_clk(clk)
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);
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localparam CLK_PERIOD = 1.0;
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always #(CLK_PERIOD/2) clk=~clk;
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initial begin
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$dumpfile("build/dump.vcd");
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$dumpvars(0, tb_adding, bep.r_registers[1]);
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end
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// should probably do more granular tests
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initial #10000 begin
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`assert(bep.r_registers[1], 64'h2020202040406090);
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$display("[ADDING] All tests passed");
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$finish;
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end
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endmodule |