memory !!
This commit is contained in:
parent
51ecf47862
commit
2e4cd0240c
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@ -52,8 +52,11 @@ fn main() {
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format!("{byte:02X}")
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}).collect();
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let bit_length = from_contents.len() * 8;
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let insert_mem = format!("reg [0:{}] mem = {bit_length}'h{mem_value};", bit_length - 1);
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let contents_len = from_contents.len() * 8;
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let bit_len = (2048 * 8).max(contents_len * 2);
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let padding_len = bit_len - contents_len;
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let insert_mem = format!("reg [0:{}] mem = {{{contents_len}'h{mem_value}, {padding_len}'h0}};", bit_len - 1);
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into_contents = into_contents.replace("$$insert_mem$$", &insert_mem);
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198
src/beepo.v
198
src/beepo.v
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@ -6,8 +6,10 @@ module Beepo #(
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) (
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input i_clk,
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input i_button1,
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input i_resume,
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output [6:0] o_segments_drive,
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output [3:0] o_displays_neg
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output [3:0] o_displays_neg,
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output o_breakpoint
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);
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// State values
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localparam IDLE = 0; // Start fetching instruction
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@ -38,8 +40,7 @@ module Beepo #(
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// Registers
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reg [63:0] r_pc = PC_START; // program counter
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reg [63:0] r_pc_latch = PC_START; // address input to ROM
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reg [63:0] r_registers [1:NUM_REGS]; // up to 255 modifiable registers
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reg [63:0] r_registers [0:NUM_REGS]; // up to 255 modifiable registers
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reg [7:0] r_instr; // the current instruction
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reg [7:0] r_arg_regs [0:3]; // register arguments
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reg [63:0] r_arg_imm = 0; // immediate argument
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@ -52,21 +53,22 @@ module Beepo #(
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reg [3:0] r_arg_current_type = 8; // the type of the current argument
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reg [5:0] r_arg_bit = 0; // the current lower bit index being fetched for the current argument
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reg r_bus_wre = 0;
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reg [7:0] r_bus_in = 0;
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reg [4:0] r_bus_bytes = 1; // the number of bytes to transfer on the bus
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reg [7:0] r_bus_index = 0; // the index of the byte in transfer
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reg [7:0] r_bus_reg = 0; // the register currently used in transfer
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reg r_bus_start = 0; // pulsed high when the bus should start a transfer
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reg r_bus_trans = 0; // trans rights (the bus is executing a transfer instruction)
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wire [63:0] w_bus_addr = r_bus_trans ? r_arg_addr : r_pc_latch;
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wire [4:0] w_bus_bytes = r_bus_trans ? r_bus_bytes : 1;
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wire [7:0] w_bus_fetch;
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reg r_mem_wre = 0;
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reg r_mem_busy = 0;
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reg r_mem_trans = 0;
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reg [7:0] r_mem_in = 0;
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reg [7:0] r_mem_index = 0; // the index of the byte in transfer
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reg [7:0] r_mem_reg = 0; // the register currently used in transfer
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wire [63:0] w_mem_addr = r_mem_trans ? r_arg_addr : r_pc;
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wire [7:0] w_mem_fetch;
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reg r_breakpoint = 0;
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assign o_breakpoint = r_breakpoint;
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genvar i;
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generate
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for (i = 1; i < NUM_REGS-1; i = i + 1) begin
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for (i = 0; i <= NUM_REGS; i = i + 1) begin
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initial r_registers[i] <= 0;
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end
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endgenerate
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@ -74,23 +76,24 @@ module Beepo #(
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always @(posedge i_clk) r_tick <= r_tick + 1;
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always @(posedge i_clk) begin
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if (w_bus_ready == 0) begin
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r_bus_start <= 0;
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r_bus_trans <= r_bus_trans & ~w_bus_ready;
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if (r_breakpoint == 1) begin
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r_breakpoint = ~i_resume;
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end else if (r_mem_busy == 1) begin
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r_mem_busy = 0;
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end else case (r_state)
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IDLE: begin
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_bus_start <= 1;
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r_state <= FETCHI;
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r_bus_wre <= 0;
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r_mem_wre <= 0;
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r_mem_busy <= 1;
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end
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FETCHI: begin
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r_instr <= w_bus_fetch;
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r_instr <= w_mem_fetch;
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r_arg_index <= 0;
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r_arg_bit <= 0;
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r_mem_trans <= 0;
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case (w_bus_fetch)
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case (w_mem_fetch)
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`TX: r_arg_types_packed = `TX_ARGS;
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`NOP: r_arg_types_packed = `NOP_ARGS;
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`ADD8: r_arg_types_packed = `ADD8_ARGS;
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@ -107,14 +110,15 @@ module Beepo #(
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`LI64: r_arg_types_packed = `LI64_ARGS;
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`LD: r_arg_types_packed = `LD_ARGS;
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`ST: r_arg_types_packed = `ST_ARGS;
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`EBP: r_arg_types_packed = `EBP_ARGS;
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default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N};
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endcase
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r_pc = r_pc + 1;
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r_mem_busy = 1;
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if (r_arg_types_packed[15:12] != ARG_N) begin
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r_state <= FETCHA;
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_bus_start <= 1;
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r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]*4+:4];
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r_arg_current_type <= r_arg_types_packed[15:12];
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@ -136,19 +140,18 @@ module Beepo #(
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if (r_arg_current_type == ARG_N) r_state <= IDLE;
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else begin
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case (r_arg_current_type)
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ARG_R: r_arg_regs[r_arg_index] <= w_bus_fetch;
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ARG_O: r_arg_addr[r_arg_bit+:8] <= w_bus_fetch;
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ARG_P: r_arg_addr[r_arg_bit+:8] <= w_bus_fetch;
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ARG_B: r_arg_imm[r_arg_bit+:8] <= w_bus_fetch;
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ARG_H: r_arg_imm[r_arg_bit+:8] <= w_bus_fetch;
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ARG_W: r_arg_imm[r_arg_bit+:8] <= w_bus_fetch;
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ARG_D: r_arg_imm[r_arg_bit+:8] <= w_bus_fetch;
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ARG_A: r_arg_addr[r_arg_bit+:8] <= w_bus_fetch;
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ARG_R: r_arg_regs[r_arg_index] <= w_mem_fetch;
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ARG_O: r_arg_addr[r_arg_bit+:8] <= w_mem_fetch;
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ARG_P: r_arg_addr[r_arg_bit+:8] <= w_mem_fetch;
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ARG_B: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
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ARG_H: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
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ARG_W: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
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ARG_D: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
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ARG_A: r_arg_addr[r_arg_bit+:8] <= w_mem_fetch;
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endcase
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_bus_start <= 1;
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r_mem_busy <= 1;
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r_arg_bytes = r_arg_bytes - 1;
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r_arg_bit <= r_arg_bit + 8;
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@ -172,82 +175,109 @@ module Beepo #(
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case (r_instr)
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`TX: r_state <= DONE;
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`NOP: ;
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`ADD8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]);
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`ADD16: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][15:0]);
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`ADD32: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][31:0]);
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`ADD64: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][63:0]);
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`ADDI8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_arg_imm[7:0]);
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`ADDI16: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_arg_imm[15:0]);
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`ADDI32: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_arg_imm[31:0]);
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`ADDI64: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_arg_imm[63:0]);
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`LI8: set_register(r_arg_regs[0], r_arg_imm);
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`LI16: set_register(r_arg_regs[0], r_arg_imm);
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`LI32: set_register(r_arg_regs[0], r_arg_imm);
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`LI64: set_register(r_arg_regs[0], r_arg_imm);
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`ADD8: set_reg_byte (r_arg_regs[0], r_registers[r_arg_regs[1]][0+:8] + r_registers [r_arg_regs[2]][0+:8]);
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`ADD16: set_reg_hword (r_arg_regs[0], r_registers[r_arg_regs[1]][0+:16] + r_registers [r_arg_regs[2]][0+:16]);
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`ADD32: set_reg_word (r_arg_regs[0], r_registers[r_arg_regs[1]][0+:32] + r_registers [r_arg_regs[2]][0+:32]);
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`ADD64: set_reg_dword (r_arg_regs[0], r_registers[r_arg_regs[1]][0+:64] + r_registers [r_arg_regs[2]][0+:64]);
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`ADDI8: set_reg_byte (r_arg_regs[0], r_registers[r_arg_regs[1]][0+:8] + r_arg_imm [0+:8]);
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`ADDI16: set_reg_hword (r_arg_regs[0], r_registers[r_arg_regs[1]][0+:16] + r_arg_imm [0+:16]);
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`ADDI32: set_reg_word (r_arg_regs[0], r_registers[r_arg_regs[1]][0+:32] + r_arg_imm [0+:32]);
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`ADDI64: set_reg_dword (r_arg_regs[0], r_registers[r_arg_regs[1]][0+:64] + r_arg_imm [0+:64]);
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`LI8: set_reg_byte (r_arg_regs[0], r_arg_imm);
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`LI16: set_reg_hword (r_arg_regs[0], r_arg_imm);
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`LI32: set_reg_word (r_arg_regs[0], r_arg_imm);
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`LI64: set_reg_dword (r_arg_regs[0], r_arg_imm);
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`LD: begin
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if (r_arg_imm > 0) begin
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r_arg_addr <= r_arg_addr + r_registers[r_arg_regs[1]];
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r_bus_index <= 0;
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r_bus_reg <= r_arg_regs[0];
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r_mem_index <= 0;
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r_mem_reg <= r_arg_regs[0];
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r_mem_busy <= 1;
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r_state <= MEMR;
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r_bus_start <= 1;
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r_bus_trans <= 1;
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r_bus_bytes <= 1;
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r_mem_trans <= 1;
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end
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end
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`ST: begin
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if (r_arg_imm > 0) begin
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r_arg_addr <= r_arg_addr + r_registers[r_arg_regs[1]];
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r_bus_index <= 0;
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r_bus_reg <= r_arg_regs[0];
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r_bus_wre <= 1;
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r_bus_in <= r_registers[r_arg_regs[0]][0+:8];
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r_mem_index <= 1;
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r_mem_reg <= r_arg_regs[0];
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r_mem_wre <= 1;
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r_mem_in <= r_registers[r_arg_regs[0]][0+:8];
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r_mem_busy <= 1;
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r_state <= MEMR;
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r_bus_start <= 1;
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r_bus_trans <= 1;
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r_bus_bytes <= 1;
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r_mem_trans <= 1;
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end
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end
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`EBP: r_breakpoint = 1;
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endcase
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end
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MEMR: begin
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case (r_instr)
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`LD: set_register(r_arg_regs[0], w_bus_fetch);
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`ST: r_bus_in <= r_registers[r_arg_regs[0]][r_bus_index];
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`LD: set_reg_part(r_mem_reg, w_mem_fetch, r_mem_index*8);
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`ST: r_mem_in <= r_registers[r_mem_reg][r_mem_index*8+:8];
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endcase
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r_mem_busy <= 1;
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if (r_arg_imm == 1) begin
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// reached the end of the transfer
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r_bus_wre <= 0;
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r_mem_wre <= 0;
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r_mem_trans <= 0;
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r_state <= FETCHI;
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end else begin
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if (r_bus_index == 6) begin
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r_mem_index = r_mem_index + 1;
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if (r_mem_index == 8) begin
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// reached the end of this register
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r_bus_reg <= r_bus_reg + 1;
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r_mem_reg <= r_mem_reg + 1;
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r_mem_index <= 0;
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end
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r_arg_addr <= r_arg_addr + 1;
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r_arg_imm <= r_arg_imm - 1;
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r_bus_start <= 1;
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r_bus_trans <= 1;
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end
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end
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endcase
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end
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task automatic set_register(
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input [7:0] being_set,
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input [63:0] setting_to
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);
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if (being_set != 0) r_registers[being_set] = setting_to;
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endtask
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always @(r_registers[0]) r_registers[0] <= 0;
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task automatic set_reg_byte(
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input [7:0] being_set,
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input [2:0] byte_idx,
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input [7:0] setting_to
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);
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if (being_set != 0) r_registers[being_set][byte_idx*8+:8] = setting_to;
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r_registers[being_set][0+:8] = setting_to;
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endtask
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task automatic set_reg_hword(
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input [7:0] being_set,
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input [15:0] setting_to
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);
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r_registers[being_set][0+:16] = setting_to;
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endtask
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task automatic set_reg_word(
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input [7:0] being_set,
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input [31:0] setting_to
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);
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r_registers[being_set][0+:32] = setting_to;
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endtask
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task automatic set_reg_dword(
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input [7:0] being_set,
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input [63:0] setting_to
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);
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r_registers[being_set][0+:64] = setting_to;
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endtask
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task automatic set_reg_part(
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input [7:0] being_set,
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input [7:0] setting_to,
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input [5:0] start_bit
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);
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if (start_bit <= 56) r_registers[being_set][start_bit+:8] = setting_to;
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endtask
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Multi7 display (
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@ -257,14 +287,14 @@ module Beepo #(
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.o_displays_neg(o_displays_neg)
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);
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Bus bus (
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.i_clk(i_clk),
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.i_addr(w_bus_addr),
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.i_in(r_bus_in),
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.i_flags(r_bus_wre),
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.i_size(r_bus_bytes),
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.i_start(r_bus_start),
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.o_ready(w_bus_ready),
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.o_out(w_bus_fetch)
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spMem mem (
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.clk(i_clk),
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.ad(w_mem_addr),
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.din(r_mem_in),
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.dout(w_mem_fetch),
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.oce(0),
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.ce(1),
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.reset(0),
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.wre(r_mem_wre)
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);
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endmodule
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@ -59,3 +59,7 @@
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// Conditional jump
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`define JEQ 'h56
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// Environment traps
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`define EBP 'h5D
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`define EBP_ARGS {ARG_N, ARG_N, ARG_N, ARG_N}
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47
tests/Makefile
Normal file
47
tests/Makefile
Normal file
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@ -0,0 +1,47 @@
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SLAPPER_DIR = ../slapper
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SLAPPER_BUILD = $(SLAPPER_DIR)/target/release/slapper
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SLAPPER = ./slapper
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HBASM = ./hbasm
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SPMEM = spmem.v
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INPUT_FILE = inputs.txt
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BUILD_DEPS = ../src/beepo.v ../src/instructions.v ../src/uart_tx.v ../src/multi7.v ../src/bus.v
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%.clean: %/build
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rm -r $<
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$(SLAPPER_BUILD): $(SLAPPER_DIR)/src/main.rs
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cargo build --manifest-path $(SLAPPER_DIR)/Cargo.toml -r
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$(SLAPPER): $(SLAPPER_BUILD)
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cp $< $@
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%/build:
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mkdir -p $@
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%/build/program.bin: %/program.rhai %/build
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$(HBASM) $< > $@
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%/build/spmem_gen.v: %/build/program.bin $(SLAPPER)
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$(SLAPPER) $< $(SPMEM) $@
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%/build/out: $(INPUT_FILE) %/$(INPUT_FILE) $(BUILD_DEPS) %/top.v %/build/spmem_gen.v
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iverilog -o $@ -c $< -c $(word 2, $^) -s tb_beepo
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%/build/dump.vcd: %/build/out
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vvp $<
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%.wave: %/build/dump.vcd
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gtkwave $<
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%.assemble: %/build/program.bin
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echo Done
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%.insert-mem: %/build/spmem_gen.v
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echo Done
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%.synth: %/build/out
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echo Done
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%.run: %/build/dump.vcd
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echo Done
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
SLAPPER_DIR = ../../slapper
|
||||
SLAPPER_BUILD = ${SLAPPER_DIR}/target/release/slapper
|
||||
SLAPPER = ../slapper
|
||||
HBASM = ../hbasm
|
||||
SPMEM = ../spmem.v
|
||||
|
||||
INPUT_FILE = inputs.txt
|
||||
BUILD_DEPS = ../../src/beepo.v ../../src/instructions.v adding.v ../../src/uart_tx.v ../../src/multi7.v ../../src/bus.v build/spmem_gen.v
|
||||
|
||||
clean:
|
||||
rm -r build
|
||||
|
||||
${SLAPPER_BUILD}:
|
||||
cargo build --manifest-path ${SLAPPER_DIR}/Cargo.toml -r
|
||||
|
||||
${SLAPPER}: ${SLAPPER_BUILD}
|
||||
cp $< $@
|
||||
|
||||
build:
|
||||
mkdir -p $@
|
||||
|
||||
build/program.bin: program.rhai | build
|
||||
${HBASM} $< > $@
|
||||
|
||||
build/spmem_gen.v: build/program.bin ${SLAPPER}
|
||||
${SLAPPER} $< ${SPMEM} $@
|
||||
|
||||
build/out: ${INPUT_FILE} ${BUILD_DEPS} build/spmem_gen.v
|
||||
iverilog -o $@ -c $< -s tb_adding
|
||||
|
||||
build/dump.vcd: build/out
|
||||
vvp $<
|
||||
|
||||
wave: build/dump.vcd
|
||||
gtkwave build/dump.vcd
|
||||
|
||||
assemble: build/program.bin
|
||||
insert-mem: build/spmem_gen.v
|
||||
synth: build/out
|
||||
run: build/dump.vcd
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
`include "../../src/beepo.v"
|
||||
`timescale 100us/10ns
|
||||
|
||||
`define assert(signal, value) \
|
||||
if (signal !== value) begin \
|
||||
$display("ASSERTION FAILED in %m: signal != value"); \
|
||||
$finish; \
|
||||
end
|
||||
|
||||
module tb_adding();
|
||||
reg clk = 0;
|
||||
|
||||
Beepo #(
|
||||
.FREQ(1),
|
||||
.UART_BAUD(1_000_000)
|
||||
) bep (
|
||||
.i_clk(clk)
|
||||
);
|
||||
|
||||
localparam CLK_PERIOD = 1.0;
|
||||
always #(CLK_PERIOD/2) clk=~clk;
|
||||
|
||||
initial begin
|
||||
$dumpfile("build/dump.vcd");
|
||||
$dumpvars(0, tb_adding,
|
||||
bep.r_arg_regs[0], bep.r_arg_regs[1],
|
||||
bep.r_arg_regs[2], bep.r_arg_regs[3],
|
||||
bep.r_registers[1]
|
||||
);
|
||||
end
|
||||
|
||||
// should probably do more granular tests
|
||||
initial #10000 begin
|
||||
`assert(bep.r_registers[1], 64'h2020202040406090);
|
||||
$display("[ADDING] All tests passed");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,6 +1,2 @@
|
|||
../../src/instructions.v
|
||||
adding.v
|
||||
../../src/uart_tx.v
|
||||
../../src/multi7.v
|
||||
../../src/bus.v
|
||||
build/spmem_gen.v
|
||||
adding/top.v
|
||||
adding/build/spmem_gen.v
|
||||
|
|
|
|||
|
|
@ -2,15 +2,18 @@ li8 (r1, 0x10);
|
|||
li16 (r2, 0x1010);
|
||||
li32 (r3, 0x10101010);
|
||||
li64 (r4, 0x1010101010101010);
|
||||
ebp();
|
||||
|
||||
add8 (r1, r1, r1);
|
||||
add16 (r1, r1, r2);
|
||||
add32 (r1, r1, r3);
|
||||
add64 (r1, r1, r4);
|
||||
add8 (r1, r1, r1); // 20
|
||||
add16 (r1, r1, r2); // 1030
|
||||
add32 (r1, r1, r3); // 10102040
|
||||
add64 (r1, r1, r4); // 1010101020203050
|
||||
ebp();
|
||||
|
||||
addi8 (r1, r1, 0x10);
|
||||
addi16 (r1, r1, 0x1010);
|
||||
addi32 (r1, r1, 0x10101010);
|
||||
addi64 (r1, r1, 0x1010101010101010);
|
||||
addi8 (r1, r1, 0x10); // 1010101020203060
|
||||
addi16 (r1, r1, 0x1010); // 1010101020204070
|
||||
addi32 (r1, r1, 0x10101010); // 1010101030305080
|
||||
addi64 (r1, r1, 0x1010101010101010); // 2020202040406090
|
||||
ebp();
|
||||
|
||||
tx();
|
||||
73
tests/adding/top.v
Normal file
73
tests/adding/top.v
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
`include "../src/beepo.v"
|
||||
`timescale 100us/10ns
|
||||
|
||||
`define assert(signal, value) \
|
||||
if (signal !== value) begin \
|
||||
$display("ASSERTION FAILED in %m: signal != value"); \
|
||||
$finish; \
|
||||
end
|
||||
|
||||
module tb_beepo();
|
||||
localparam T_LI = 0;
|
||||
localparam T_ADD = 1;
|
||||
localparam T_ADDI = 2;
|
||||
|
||||
reg r_clk = 0;
|
||||
reg r_resume = 0;
|
||||
reg [1:0] r_test = 0;
|
||||
|
||||
wire w_breakpoint;
|
||||
|
||||
Beepo #(
|
||||
.FREQ(1)
|
||||
) bep (
|
||||
.i_clk(r_clk),
|
||||
.i_resume(r_resume),
|
||||
.o_breakpoint(w_breakpoint)
|
||||
);
|
||||
|
||||
localparam CLK_PERIOD = 1.0;
|
||||
always #(CLK_PERIOD/2) r_clk=~r_clk;
|
||||
|
||||
initial begin
|
||||
$dumpfile("adding/build/dump.vcd");
|
||||
$dumpvars(0, tb_beepo,
|
||||
bep.r_arg_regs[0], bep.r_arg_regs[1],
|
||||
bep.r_arg_regs[2], bep.r_arg_regs[3],
|
||||
bep.r_registers[1], bep.r_registers[3]
|
||||
);
|
||||
end
|
||||
|
||||
// should probably do more granular tests
|
||||
always @(posedge w_breakpoint) begin
|
||||
$display("BREAK");
|
||||
case (r_test)
|
||||
T_LI: begin
|
||||
`assert(bep.r_registers[1], 64'h10);
|
||||
`assert(bep.r_registers[2], 64'h1010);
|
||||
`assert(bep.r_registers[3], 64'h10101010);
|
||||
`assert(bep.r_registers[4], 64'h1010101010101010);
|
||||
$display("[ADDING] LI tests passed");
|
||||
end
|
||||
T_ADD: begin
|
||||
`assert(bep.r_registers[1], 64'h1010101020203050);
|
||||
$display("[ADDING] ADD test passed");
|
||||
end
|
||||
T_ADDI: begin
|
||||
`assert(bep.r_registers[1], 64'h2020202040406090);
|
||||
$display("[ADDING] ADDI test passed");
|
||||
$display("[ADDING] All tests passed");
|
||||
$finish;
|
||||
end
|
||||
endcase
|
||||
|
||||
r_test <= r_test + 1;
|
||||
r_resume = 1;
|
||||
#2 r_resume = 0;
|
||||
end
|
||||
|
||||
initial #100000 begin
|
||||
$display("[ADDING] Timeout");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
33
tests/gtkw_filters/arg_types.py
Executable file
33
tests/gtkw_filters/arg_types.py
Executable file
|
|
@ -0,0 +1,33 @@
|
|||
#!/usr/bin/env python3
|
||||
import sys
|
||||
|
||||
arg_types = {
|
||||
"0": "R",
|
||||
"1": "O",
|
||||
"2": "P",
|
||||
"3": "B",
|
||||
"4": "H",
|
||||
"5": "W",
|
||||
"6": "D",
|
||||
"7": "A",
|
||||
"8": "N"
|
||||
}
|
||||
|
||||
def main():
|
||||
fh_in = sys.stdin
|
||||
fh_out = sys.stdout
|
||||
|
||||
while True:
|
||||
# incoming values have newline
|
||||
l = fh_in.readline()
|
||||
if not l:
|
||||
return 0
|
||||
|
||||
for arg_id in arg_types:
|
||||
l = l.replace(arg_id, arg_types[arg_id])
|
||||
|
||||
fh_out.write(l)
|
||||
fh_out.flush()
|
||||
|
||||
if __name__ == '__main__':
|
||||
sys.exit(main())
|
||||
43
tests/gtkw_filters/r_instr.py
Executable file
43
tests/gtkw_filters/r_instr.py
Executable file
|
|
@ -0,0 +1,43 @@
|
|||
#!/usr/bin/env python3
|
||||
import sys
|
||||
|
||||
instructions = {
|
||||
0x00: "UN",
|
||||
0x01: "TX",
|
||||
0x02: "NOP",
|
||||
0x03: "ADD8",
|
||||
0x04: "ADD16",
|
||||
0x05: "ADD32",
|
||||
0x06: "ADD64",
|
||||
0x2D: "ADDI8",
|
||||
0x2E: "ADDI16",
|
||||
0x2F: "ADDI32",
|
||||
0x30: "ADDI64",
|
||||
0x48: "LI8",
|
||||
0x49: "LI16",
|
||||
0x4A: "LI32",
|
||||
0x4B: "LI64",
|
||||
0x4D: "LD",
|
||||
0x4E: "ST",
|
||||
0x5D: "EBP"
|
||||
}
|
||||
|
||||
def main():
|
||||
fh_in = sys.stdin
|
||||
fh_out = sys.stdout
|
||||
|
||||
while True:
|
||||
# incoming values have newline
|
||||
l = fh_in.readline()
|
||||
if not l:
|
||||
return 0
|
||||
|
||||
if "x" in l.lower() or "z" in l.lower():
|
||||
fh_out.write(l)
|
||||
else:
|
||||
fh_out.write(f"{instructions.get(int(l, 16))}\n")
|
||||
|
||||
fh_out.flush()
|
||||
|
||||
if __name__ == '__main__':
|
||||
sys.exit(main())
|
||||
36
tests/gtkw_filters/state.py
Executable file
36
tests/gtkw_filters/state.py
Executable file
|
|
@ -0,0 +1,36 @@
|
|||
#!/usr/bin/env python3
|
||||
import sys
|
||||
|
||||
states = [
|
||||
"IDLE",
|
||||
"FETCHI",
|
||||
"FETCHA",
|
||||
"EXEC",
|
||||
"MEMR",
|
||||
"DONE"
|
||||
]
|
||||
|
||||
def main():
|
||||
fh_in = sys.stdin
|
||||
fh_out = sys.stdout
|
||||
|
||||
while True:
|
||||
# incoming values have newline
|
||||
l = fh_in.readline()
|
||||
if not l:
|
||||
return 0
|
||||
|
||||
num = int(l, 16)
|
||||
|
||||
if "x" in l.lower() or "z" in l.lower():
|
||||
fh_out.write(l)
|
||||
else:
|
||||
if num >= len(states):
|
||||
fh_out.write(l)
|
||||
else:
|
||||
fh_out.write(f"{states[num]}\n")
|
||||
|
||||
fh_out.flush()
|
||||
|
||||
if __name__ == '__main__':
|
||||
sys.exit(main())
|
||||
4
tests/inputs.txt
Normal file
4
tests/inputs.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
../src/instructions.v
|
||||
../src/uart_tx.v
|
||||
../src/multi7.v
|
||||
../src/bus.v
|
||||
2
tests/mem/inputs.txt
Normal file
2
tests/mem/inputs.txt
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
mem/top.v
|
||||
mem/build/spmem_gen.v
|
||||
13
tests/mem/program.rhai
Normal file
13
tests/mem/program.rhai
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
li64 (r4, 0x1020304050607080);
|
||||
st (r4, r0, 0x400, 8);
|
||||
ld (r1, r0, 0x400, 8); // 0x1020304050607080
|
||||
ebp();
|
||||
|
||||
ld (r2, r0, 0x404, 4); // 0x0000000010203040
|
||||
ebp();
|
||||
|
||||
li64 (r1, 0x1010202030304040);
|
||||
li64 (r2, 0x5050606070708080);
|
||||
st (r1, r0, 0x410, 16);
|
||||
ld (r3, r0, 0x410, 16);
|
||||
ebp();
|
||||
78
tests/mem/top.v
Normal file
78
tests/mem/top.v
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
`include "../src/beepo.v"
|
||||
`timescale 100us/10ns
|
||||
|
||||
`define assert(signal, value) \
|
||||
if (signal !== value) begin \
|
||||
$display("ASSERTION FAILED in %m: signal != value"); \
|
||||
$finish; \
|
||||
end
|
||||
|
||||
module tb_beepo();
|
||||
localparam T_STLD = 0;
|
||||
localparam T_STLD_HALF = 1;
|
||||
localparam T_STLD_DOUBLE = 2;
|
||||
|
||||
localparam T_TESTS = 3;
|
||||
|
||||
reg r_clk = 0;
|
||||
reg r_resume = 0;
|
||||
reg [1:0] r_test = 0;
|
||||
|
||||
wire w_breakpoint;
|
||||
|
||||
Beepo #(
|
||||
.FREQ(1)
|
||||
) bep (
|
||||
.i_clk(r_clk),
|
||||
.i_resume(r_resume),
|
||||
.o_breakpoint(w_breakpoint)
|
||||
);
|
||||
|
||||
localparam CLK_PERIOD = 1.0;
|
||||
always #(CLK_PERIOD/2) r_clk=~r_clk;
|
||||
|
||||
initial begin
|
||||
$dumpfile("mem/build/dump.vcd");
|
||||
$dumpvars(0, tb_beepo,
|
||||
bep.r_arg_regs[0], bep.r_arg_regs[1],
|
||||
bep.r_arg_regs[2], bep.r_arg_regs[3],
|
||||
bep.r_registers[1], bep.r_registers[2],
|
||||
bep.r_registers[3], bep.r_registers[4]
|
||||
);
|
||||
end
|
||||
|
||||
// should probably do more granular tests
|
||||
always @(posedge w_breakpoint) begin
|
||||
$display("BREAK");
|
||||
case (r_test)
|
||||
T_STLD: begin
|
||||
`assert(bep.r_registers[1], 64'h1020304050607080);
|
||||
$display("[MEM] ST/LD test passed");
|
||||
end
|
||||
T_STLD_HALF: begin
|
||||
`assert(bep.r_registers[2], 64'h0000000010203040);
|
||||
$display("[MEM] ST/LD Half test passed");
|
||||
end
|
||||
T_STLD_DOUBLE: begin
|
||||
`assert(bep.r_registers[3], 64'h1010202030304040);
|
||||
`assert(bep.r_registers[4], 64'h5050606070708080);
|
||||
$display("[MEM] ST/LD Double test passed");
|
||||
end
|
||||
endcase
|
||||
|
||||
r_test = r_test + 1;
|
||||
|
||||
if (r_test == T_TESTS) begin
|
||||
$display("[MEM] All tests passed");
|
||||
$finish;
|
||||
end
|
||||
|
||||
r_resume = 1;
|
||||
#2 r_resume = 0;
|
||||
end
|
||||
|
||||
initial #100000 begin
|
||||
$display("[ADDING] Timeout");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -18,7 +18,11 @@ module spMem(
|
|||
|
||||
always @(negedge clk) begin
|
||||
// one full clock cycle before being fetched
|
||||
if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
|
||||
if (r_ad_prev == ad) begin
|
||||
if (wre == 1) mem[ad*8+:8] = din;
|
||||
r_out <= mem[ad*8+:8];
|
||||
|
||||
end
|
||||
else r_ad_prev = ad;
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in a new issue