heck
This commit is contained in:
parent
0794824fcd
commit
51ecf47862
144
src/beepo.v
144
src/beepo.v
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@ -14,6 +14,7 @@ module Beepo #(
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localparam FETCHI = 1; // Instruction is fetched, start fetching first argument
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localparam FETCHA = 2; // Argument byte is fetched
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localparam EXEC = 3; // Start running
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localparam MEMR = 4; // Transferring bytes between memory and registers
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localparam DONE = 7; // Done executing
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// Argument types
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@ -33,13 +34,12 @@ module Beepo #(
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localparam NUM_REGS = 4;
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reg [2:0] r_state = IDLE;
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reg r_fetching = 0; // counter for waiting before reading from memory
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reg [63:0] r_tick = 0;
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// Registers
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reg [63:0] r_pc = PC_START; // program counter
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reg [63:0] r_pc_latch = PC_START; // address input to ROM
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reg [63:0] r_registers [0:NUM_REGS]; // up to 255 modifiable registers
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reg [63:0] r_registers [1:NUM_REGS]; // up to 255 modifiable registers
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reg [7:0] r_instr; // the current instruction
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reg [7:0] r_arg_regs [0:3]; // register arguments
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reg [63:0] r_arg_imm = 0; // immediate argument
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@ -52,7 +52,16 @@ module Beepo #(
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reg [3:0] r_arg_current_type = 8; // the type of the current argument
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reg [5:0] r_arg_bit = 0; // the current lower bit index being fetched for the current argument
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wire [7:0] w_mem_fetch;
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reg r_bus_wre = 0;
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reg [7:0] r_bus_in = 0;
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reg [4:0] r_bus_bytes = 1; // the number of bytes to transfer on the bus
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reg [7:0] r_bus_index = 0; // the index of the byte in transfer
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reg [7:0] r_bus_reg = 0; // the register currently used in transfer
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reg r_bus_start = 0; // pulsed high when the bus should start a transfer
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reg r_bus_trans = 0; // trans rights (the bus is executing a transfer instruction)
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wire [63:0] w_bus_addr = r_bus_trans ? r_arg_addr : r_pc_latch;
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wire [4:0] w_bus_bytes = r_bus_trans ? r_bus_bytes : 1;
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wire [7:0] w_bus_fetch;
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genvar i;
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@ -65,20 +74,23 @@ module Beepo #(
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always @(posedge i_clk) r_tick <= r_tick + 1;
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always @(posedge i_clk) begin
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if (r_fetching) r_fetching <= r_fetching + 1;
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else case (r_state)
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if (w_bus_ready == 0) begin
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r_bus_start <= 0;
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r_bus_trans <= r_bus_trans & ~w_bus_ready;
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end else case (r_state)
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IDLE: begin
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_fetching <= 1;
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r_bus_start <= 1;
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r_state <= FETCHI;
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r_bus_wre <= 0;
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end
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FETCHI: begin
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r_instr <= w_mem_fetch;
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r_instr <= w_bus_fetch;
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r_arg_index <= 0;
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r_arg_bit <= 0;
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case (w_mem_fetch)
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case (w_bus_fetch)
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`TX: r_arg_types_packed = `TX_ARGS;
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`NOP: r_arg_types_packed = `NOP_ARGS;
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`ADD8: r_arg_types_packed = `ADD8_ARGS;
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@ -93,6 +105,8 @@ module Beepo #(
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`LI16: r_arg_types_packed = `LI16_ARGS;
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`LI32: r_arg_types_packed = `LI32_ARGS;
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`LI64: r_arg_types_packed = `LI64_ARGS;
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`LD: r_arg_types_packed = `LD_ARGS;
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`ST: r_arg_types_packed = `ST_ARGS;
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default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N};
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endcase
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@ -100,7 +114,7 @@ module Beepo #(
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r_state <= FETCHA;
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_fetching <= 1;
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r_bus_start <= 1;
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r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]*4+:4];
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r_arg_current_type <= r_arg_types_packed[15:12];
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@ -122,19 +136,19 @@ module Beepo #(
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if (r_arg_current_type == ARG_N) r_state <= IDLE;
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else begin
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case (r_arg_current_type)
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ARG_R: r_arg_regs[r_arg_index] <= w_mem_fetch;
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ARG_O: r_arg_addr[r_arg_bit+:8] <= w_mem_fetch;
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ARG_P: r_arg_addr[r_arg_bit+:8] <= w_mem_fetch;
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ARG_B: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
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ARG_H: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
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ARG_W: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
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ARG_D: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
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ARG_A: r_arg_addr[r_arg_bit+:8] <= w_mem_fetch;
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ARG_R: r_arg_regs[r_arg_index] <= w_bus_fetch;
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ARG_O: r_arg_addr[r_arg_bit+:8] <= w_bus_fetch;
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ARG_P: r_arg_addr[r_arg_bit+:8] <= w_bus_fetch;
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ARG_B: r_arg_imm[r_arg_bit+:8] <= w_bus_fetch;
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ARG_H: r_arg_imm[r_arg_bit+:8] <= w_bus_fetch;
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ARG_W: r_arg_imm[r_arg_bit+:8] <= w_bus_fetch;
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ARG_D: r_arg_imm[r_arg_bit+:8] <= w_bus_fetch;
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ARG_A: r_arg_addr[r_arg_bit+:8] <= w_bus_fetch;
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endcase
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_fetching <= 1;
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r_bus_start <= 1;
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r_arg_bytes = r_arg_bytes - 1;
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r_arg_bit <= r_arg_bit + 8;
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@ -143,21 +157,11 @@ module Beepo #(
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r_arg_index = r_arg_index + 1;
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r_arg_current_type = r_arg_types[r_arg_index];
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if (r_arg_current_type == ARG_N) r_state <= EXEC;
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// Execute when there is no next argument or r_arg_index has overflowed
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if (r_arg_current_type == ARG_N || r_arg_index == 0) r_state <= EXEC;
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else begin
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r_arg_bit <= 0;
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r_arg_bit <= 0;
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r_arg_bytes <= ARG_SIZES[r_arg_current_type*4+:4];
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case (r_arg_current_type)
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ARG_R: r_arg_regs[r_arg_index] <= 0;
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ARG_O: r_arg_addr[r_arg_bit-1] <= 0;
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ARG_P: r_arg_addr[r_arg_bit-1] <= 0;
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ARG_B: r_arg_imm[r_arg_bit-1] <= 0;
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ARG_H: r_arg_imm[r_arg_bit-1] <= 0;
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ARG_W: r_arg_imm[r_arg_bit-1] <= 0;
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ARG_D: r_arg_imm[r_arg_bit-1] <= 0;
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ARG_A: r_arg_addr[r_arg_bit-1] <= 0;
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endcase
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end
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end
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end
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@ -180,13 +184,57 @@ module Beepo #(
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`LI16: set_register(r_arg_regs[0], r_arg_imm);
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`LI32: set_register(r_arg_regs[0], r_arg_imm);
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`LI64: set_register(r_arg_regs[0], r_arg_imm);
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`LD: begin
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if (r_arg_imm > 0) begin
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r_arg_addr <= r_arg_addr + r_registers[r_arg_regs[1]];
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r_bus_index <= 0;
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r_bus_reg <= r_arg_regs[0];
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r_state <= MEMR;
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r_bus_start <= 1;
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r_bus_trans <= 1;
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r_bus_bytes <= 1;
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end
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end
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`ST: begin
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if (r_arg_imm > 0) begin
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r_arg_addr <= r_arg_addr + r_registers[r_arg_regs[1]];
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r_bus_index <= 0;
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r_bus_reg <= r_arg_regs[0];
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r_bus_wre <= 1;
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r_bus_in <= r_registers[r_arg_regs[0]][0+:8];
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r_state <= MEMR;
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r_bus_start <= 1;
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r_bus_trans <= 1;
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r_bus_bytes <= 1;
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end
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end
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endcase
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end
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MEMR: begin
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case (r_instr)
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`LD: set_register(r_arg_regs[0], w_bus_fetch);
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`ST: r_bus_in <= r_registers[r_arg_regs[0]][r_bus_index];
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endcase
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if (r_arg_imm == 1) begin
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// reached the end of the transfer
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r_bus_wre <= 0;
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r_state <= FETCHI;
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end else begin
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if (r_bus_index == 6) begin
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// reached the end of this register
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r_bus_reg <= r_bus_reg + 1;
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end
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r_arg_addr <= r_arg_addr + 1;
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r_arg_imm <= r_arg_imm - 1;
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r_bus_start <= 1;
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r_bus_trans <= 1;
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end
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end
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endcase
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end
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task automatic set_register(
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input [7:0] being_set,
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input [63:0] setting_to
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@ -194,23 +242,29 @@ module Beepo #(
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if (being_set != 0) r_registers[being_set] = setting_to;
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endtask
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task automatic set_reg_byte(
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input [7:0] being_set,
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input [2:0] byte_idx,
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input [7:0] setting_to
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);
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if (being_set != 0) r_registers[being_set][byte_idx*8+:8] = setting_to;
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endtask
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Multi7 display (
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.i_clk(i_clk),
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.i_hex({r_registers[1][15:0]}),
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.o_segments_drive(o_segments_drive),
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.o_displays_neg(o_displays_neg)
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);
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// TODO: Bus
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// For now this is just ROM
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spMem memory (
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.dout(w_mem_fetch), //output [7:0] dout
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.clk(i_clk), //input clk
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.oce(1'b0), //input oce (unused)
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.ce(1'b1), //input ce
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.reset(1'b0), //input reset
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.wre(1'b0), //input wre (write enable)
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.ad(r_pc_latch[0+:32]), //input [15:0] ad
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.din(1'b0) //input [7:0] din
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Bus bus (
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.i_clk(i_clk),
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.i_addr(w_bus_addr),
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.i_in(r_bus_in),
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.i_flags(r_bus_wre),
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.i_size(r_bus_bytes),
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.i_start(r_bus_start),
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.o_ready(w_bus_ready),
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.o_out(w_bus_fetch)
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);
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endmodule
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71
src/bus.v
Normal file
71
src/bus.v
Normal file
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@ -0,0 +1,71 @@
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// To read:
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// 1. Set i_addr to start address
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// 2. Set i_flags.0 to 0
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// 3. Set i_size to number of bytes to read
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// 4. Pulse i_start high
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// 5. When o_ready goes high, the read data will be in o_out
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// To write:
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// 1. Set i_addr to start address
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// 2. Set i_in to the data to write
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// 3. Set i_flags.0 to 1
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// 4. Pulse i_start high
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// 5. When o_ready goes high, the transfer is complete
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module Bus#(
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parameter ADDR_WIDTH = 16,
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parameter DATA_WIDTH = 256
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) (
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input i_clk,
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input [ADDR_WIDTH-1:0] i_addr,
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input [DATA_WIDTH-1:0] i_in,
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input [0:0] i_flags, // flags.0: read(0)/write(1)
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input [5:0] i_size,
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input i_start, // pulsed high to start transfer
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output o_ready,
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output [DATA_WIDTH-1:0] o_out
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);
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localparam F_READ = 'b0;
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localparam F_WRITE = 'b1;
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localparam S_IDLE = 0;
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localparam S_BUSY = 1;
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reg r_status = S_IDLE;
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reg r_enable = 0;
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reg [5:0] r_tx_size = 0;
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reg [5:0] r_byte_index = 0;
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reg [7:0] r_in = 0;
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reg [ADDR_WIDTH-1:0] r_mem_addr;
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assign o_ready = r_byte_index == 0 || r_byte_index > r_tx_size;
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always @(posedge i_clk or posedge i_start) begin
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if (i_start && !r_enable) begin
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r_mem_addr <= i_addr;
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r_enable <= 1;
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r_status <= S_BUSY;
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r_tx_size <= i_size;
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r_in <= i_in[0+:8];
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r_byte_index <= 1; // 0 is transferring now
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end else if (r_status == S_BUSY) r_status <= S_IDLE;
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else if (r_enable && r_byte_index > r_tx_size) r_enable <= 0;
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else if (r_enable) begin
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// increment address, input next byte
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r_mem_addr <= r_mem_addr + 1;
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r_status <= S_BUSY;
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r_in <= i_in[r_byte_index*8+:8];
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r_byte_index <= r_byte_index + 1;
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end
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end
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spMem memory (
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.dout(o_out), //output [7:0] dout
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.clk(i_clk), //input clk
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.oce(1'b0), //input oce (unused)
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.ce(r_enable), //input ce
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.reset(1'b0), //input reset
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.wre(i_flags[0]), //input wre (write enable)
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.ad(r_mem_addr), //input [15:0] ad
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.din(r_in) //input [7:0] din
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);
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endmodule
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@ -51,5 +51,11 @@
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`define LI64 'h4B
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`define LI64_ARGS {ARG_R, ARG_D, ARG_N, ARG_N}
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// Absolute addresing memory access operations
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`define LD 'h4D
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`define LD_ARGS {ARG_R, ARG_R, ARG_A, ARG_H}
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`define ST 'h4E
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`define ST_ARGS {ARG_R, ARG_R, ARG_A, ARG_H}
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// Conditional jump
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`define JEQ 'h56
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@ -5,8 +5,10 @@ HBASM = ../hbasm
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SPMEM = ../spmem.v
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INPUT_FILE = inputs.txt
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BUILD_DEPS = ../../src/beepo.v ../../src/instructions.v adding.v ../../src/uart_tx.v ../../src/multi7.v build/spmem_gen.v
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BUILD_DEPS = ../../src/beepo.v ../../src/instructions.v adding.v ../../src/uart_tx.v ../../src/multi7.v ../../src/bus.v build/spmem_gen.v
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clean:
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rm -r build
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${SLAPPER_BUILD}:
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cargo build --manifest-path ${SLAPPER_DIR}/Cargo.toml -r
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@ -34,5 +36,5 @@ wave: build/dump.vcd
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assemble: build/program.bin
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insert-mem: build/spmem_gen.v
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synthesize: build/out
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run: build/dump.vcd
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synth: build/out
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run: build/dump.vcd
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@ -22,7 +22,11 @@ module tb_adding();
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initial begin
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$dumpfile("build/dump.vcd");
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$dumpvars(0, tb_adding, bep.r_registers[1]);
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$dumpvars(0, tb_adding,
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bep.r_arg_regs[0], bep.r_arg_regs[1],
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bep.r_arg_regs[2], bep.r_arg_regs[3],
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bep.r_registers[1]
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);
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end
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// should probably do more granular tests
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@ -2,4 +2,5 @@
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adding.v
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../../src/uart_tx.v
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../../src/multi7.v
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../../src/bus.v
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build/spmem_gen.v
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