gwwaaagghhhh
This commit is contained in:
parent
42e13aa3ae
commit
ce32cfd5fb
4
.gitignore
vendored
4
.gitignore
vendored
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@ -1,2 +1,4 @@
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impl/
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**/*.gprj
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**/*.gprj
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tests/*.vcd
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tests/out
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4
Makefile
Normal file
4
Makefile
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BOARD = tangnano20k
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flash:
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openFPGALoader -m -b ${BOARD} impl/pnr/*.fs
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24
holeybeepo.gprj.user
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24
holeybeepo.gprj.user
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<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE ProjectUserData>
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<UserConfig>
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<Version>1.0</Version>
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<FlowState>
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<Process ID="Synthesis" State="2"/>
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<Process ID="Pnr" State="4"/>
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<Process ID="Gao" State="4"/>
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<Process ID="Rtl_Gao" State="2"/>
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</FlowState>
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<ResultFileList>
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<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/holeybeepo.vg"/>
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<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/holeybeepo.fs"/>
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<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/holeybeepo.pin.html"/>
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<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/holeybeepo.db"/>
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<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/holeybeepo.power.html"/>
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<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/holeybeepo.rpt.html"/>
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<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/holeybeepo.timing_paths"/>
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<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/holeybeepo.tr.html"/>
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<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/holeybeepo_syn.rpt.html"/>
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<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/holeybeepo_syn_rsc.xml"/>
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</ResultFileList>
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<Ui>000000ff00000001fd00000002000000000000010000000250fc0200000001fc00000038000002500000008a01000018fa000000000200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000005600fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005200fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc0000000000000776000000a500fffffffa000000000100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004700fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a500fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000000006700000025000000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000ffffffff0100000207ffffffff0000000000000000</Ui>
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</UserConfig>
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190
src/beepo.v
190
src/beepo.v
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// `include "instructions.v"
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module Beepo #(
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parameter FREQ = 27_000_000
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) (
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input i_clk,
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input i_button1,
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output o_uart_tx
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);
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// State values
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localparam IDLE = 0; // Start fetching instruction
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localparam FETCHI = 1; // Instruction is fetched, start fetching first argument
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localparam FETCHA = 2; // Argument byte is fetched
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localparam EXEC = 3; // Start running
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// Argument types
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localparam [3:0] ARG_R = 0; // Register
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localparam [3:0] ARG_O = 1; // 32 bit relative PC offset
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localparam [3:0] ARG_P = 2; // 16 bit relative PC offset
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localparam [3:0] ARG_B = 3; // Byte, 8 bit
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localparam [3:0] ARG_H = 4; // Half-word, 16 bit
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localparam [3:0] ARG_W = 5; // Word, 32 bit
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localparam [3:0] ARG_D = 6; // D{gtkwave NET OFF} ouble-word, 64 bit
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localparam [3:0] ARG_A = 7; // Absolute address immediate, 64 bit
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localparam [3:0] ARG_N = 8; // No argument
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localparam [0:31] ARG_SIZES = {4'd1, 4'd4, 4'd2, 4'd1, 4'd2, 4'd4, 4'd8, 4'd8};
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localparam PC_START = 1;
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localparam NUM_REGS = 4;
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reg [2:0] r_state = IDLE;
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// UART tx
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reg [7:0] r_tx_data = 0;
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reg r_tx_send = 1;
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wire w_tx_ready;
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// Registers
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reg [63:0] r_pc = PC_START; // program counter
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reg [63:0] r_pc_latch = PC_START; // address input to ROM
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reg [63:0] r_registers [0:NUM_REGS-1]; // the 255 modifiable registers
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reg [7:0] r_instr; // the current instruction
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reg [7:0] r_arg_regs [0:3]; // register arguments
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reg [63:0] r_arg_imm = 0; // immediate argument
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reg [63:0] r_arg_addr = 0; // relative/absolute address argument
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reg [1:0] r_arg_index = 3; // the instruction index currently being fetched
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reg [3:0] r_arg_types [0:3]; // the types of each argument to be fetched
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reg [15:0] r_arg_types_packed = 0; // to be unpacked into r_arg_types
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reg [2:0] r_arg_bytes = 0; // the number of bytes left to fetch for the current argument
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reg [3:0] r_arg_current_type = 8; // the type of the current argument
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reg [5:0] r_arg_bit = 0; // the current lower bit index being fetched for the current argument
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wire [7:0] w_mem_fetch;
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genvar i;
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generate
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for (i = 1; i < NUM_REGS-1; i = i + 1) begin
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initial r_registers[i] <= 0;
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end
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endgenerate
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always @(r_registers[1]) r_tx_data <= r_registers[1];
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always @(posedge i_clk) begin
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case (r_state)
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IDLE: begin
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r_pc_latch = r_pc;
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r_pc = r_pc + 1;
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r_state <= FETCHI;
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end
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FETCHI: begin
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r_instr <= w_mem_fetch;
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r_arg_index <= 0;
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r_arg_bit <= 0;
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case (w_mem_fetch)
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`ADD8: r_arg_types_packed = `ADD8_ARGS;
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`LI8: r_arg_types_packed = `LI8_ARGS;
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default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N};
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endcase
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if (r_arg_types_packed[15:12] != ARG_N) begin
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r_state <= FETCHA;
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]+:4];
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r_arg_current_type <= r_arg_types_packed[15:12];
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r_arg_types[0] <= r_arg_types_packed[15:12];
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r_arg_types[1] <= r_arg_types_packed[11:8];
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r_arg_types[2] <= r_arg_types_packed[7:4];
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r_arg_types[3] <= r_arg_types_packed[3:0];
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r_arg_regs[0] <= 0;
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r_arg_regs[1] <= 0;
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r_arg_regs[2] <= 0;
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r_arg_regs[3] <= 0;
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r_arg_imm <= 0;
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r_arg_addr <= 0;
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end else r_state <= EXEC;
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end
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FETCHA: begin
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if (r_arg_current_type == ARG_N) r_state <= IDLE;
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else begin
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case (r_arg_current_type)
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ARG_R: r_arg_regs[r_arg_index] <= w_mem_fetch;
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ARG_O: r_arg_addr[r_arg_bit-1+:8] <= w_mem_fetch;
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ARG_P: r_arg_addr[r_arg_bit-1+:8] <= w_mem_fetch;
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ARG_B: r_arg_imm[r_arg_bit-1+:8] <= w_mem_fetch;
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ARG_H: r_arg_imm[r_arg_bit-1+:8] <= w_mem_fetch;
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ARG_W: r_arg_imm[r_arg_bit-1+:8] <= w_mem_fetch;
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ARG_D: r_arg_imm[r_arg_bit-1+:8] <= w_mem_fetch;
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ARG_A: r_arg_addr[r_arg_bit-1+:8] <= w_mem_fetch;
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endcase
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_arg_bytes = r_arg_bytes - 1;
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r_arg_bit <= r_arg_bit + 8;
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if (r_arg_bytes == 0) begin
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r_arg_index = r_arg_index + 1;
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r_arg_current_type = r_arg_types[r_arg_index];
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if (r_arg_current_type == ARG_N) r_state <= EXEC;
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else begin
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r_arg_bit <= 0;
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r_arg_bytes <= ARG_SIZES[r_arg_current_type+:4];
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case (r_arg_current_type)
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ARG_R: r_arg_regs[r_arg_index] <= 0;
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ARG_O: r_arg_addr[r_arg_bit-1] <= 0;
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ARG_P: r_arg_addr[r_arg_bit-1] <= 0;
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ARG_B: r_arg_imm[r_arg_bit-1] <= 0;
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ARG_H: r_arg_imm[r_arg_bit-1] <= 0;
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ARG_W: r_arg_imm[r_arg_bit-1] <= 0;
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ARG_D: r_arg_imm[r_arg_bit-1] <= 0;
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ARG_A: r_arg_addr[r_arg_bit-1] <= 0;
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endcase
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end
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end
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end
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end
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EXEC: begin
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case (r_instr)
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`ADD8: set_register(r_arg_regs[0], r_arg_regs[1] + r_arg_regs[2][7:0]);
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`LI8: set_register(r_arg_regs[0], r_arg_imm);
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endcase
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r_state <= IDLE;
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end
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endcase
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end
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task automatic set_register(
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input [7:0] being_set,
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input [63:0] setting_to
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);
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if (being_set != 0) r_registers[being_set] <= setting_to;
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endtask
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uart_tx #(
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.CLK_FRE(FREQ / 1_000_000),
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.BAUD_RATE(115200)
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) tx (
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.clk(i_clk),
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.rst_n(1'b1),
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.tx_data(r_tx_data),
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.tx_data_valid(r_tx_send),
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.tx_data_ready(w_tx_ready),
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.tx_pin(o_uart_tx)
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);
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// TODO: Bus
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// For now this is just ROM
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spMem memory (
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.dout(w_mem_fetch), //output [7:0] dout
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.clk(i_clk), //input clk
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.oce(1'b0), //input oce (unused)
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.ce(1'b1), //input ce
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.reset(1'b0), //input reset
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.wre(1'b0), //input wre (write enable)
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.ad(r_pc_latch[31:0]), //input [15:0] ad
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.din(1'b0) //input [7:0] din
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);
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endmodule
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259
src/first.mi
Normal file
259
src/first.mi
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#File_format=Bin
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#Address_depth=65536
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#Data_width=8
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00000000
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01001000
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00000001
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00100011
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01001000
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00000010
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01000110
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00000011
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00000001
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00000001
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00000010
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00000000
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17
src/gowin_sp/gowin_sp.ipc
Normal file
17
src/gowin_sp/gowin_sp.ipc
Normal file
|
|
@ -0,0 +1,17 @@
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[General]
|
||||
ipc_version=4
|
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file=gowin_sp
|
||||
module=spMem
|
||||
target_device=gw2ar18c-000
|
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type=ram_sp
|
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version=3.0
|
||||
|
||||
[Config]
|
||||
BYTE_SIZE=0
|
||||
DEPTH=65536
|
||||
LANG=0
|
||||
READ=0
|
||||
RESET_MODE=true
|
||||
WIDTH=8
|
||||
WRITE=0
|
||||
MEM_FILE=../first.mi
|
||||
18
src/gowin_sp/gowin_sp.mod
Normal file
18
src/gowin_sp/gowin_sp.mod
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
-series GW2AR
|
||||
-device GW2AR-18
|
||||
-device_version C
|
||||
-package QFN88
|
||||
-part_number GW2AR-LV18QN88C8/I7
|
||||
|
||||
|
||||
-mod_name spMem
|
||||
-file_name gowin_sp
|
||||
-path /home/bee/Projects/holeybeepo/src/gowin_sp/
|
||||
-type RAM_SP
|
||||
-file_type vlg
|
||||
-depth 65536
|
||||
-width 8
|
||||
-read_mode bypass
|
||||
-write_mode normal
|
||||
-reset_mode sync
|
||||
-init_file /home/bee/Projects/holeybeepo/src/first.mi
|
||||
849
src/gowin_sp/gowin_sp.v
Normal file
849
src/gowin_sp/gowin_sp.v
Normal file
|
|
@ -0,0 +1,849 @@
|
|||
//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
|
||||
//All rights reserved.
|
||||
//File Title: IP file
|
||||
//GOWIN Version: V1.9.9 Beta-4 Education
|
||||
//Part Number: GW2AR-LV18QN88C8/I7
|
||||
//Device: GW2AR-18
|
||||
//Device Version: C
|
||||
//Created Time: Wed Nov 15 04:42:39 2023
|
||||
|
||||
module spMem (dout, clk, oce, ce, reset, wre, ad, din);
|
||||
|
||||
output [7:0] dout;
|
||||
input clk;
|
||||
input oce;
|
||||
input ce;
|
||||
input reset;
|
||||
input wre;
|
||||
input [15:0] ad;
|
||||
input [7:0] din;
|
||||
|
||||
wire [30:0] sp_inst_0_dout_w;
|
||||
wire [0:0] sp_inst_0_dout;
|
||||
wire [30:0] sp_inst_1_dout_w;
|
||||
wire [0:0] sp_inst_1_dout;
|
||||
wire [30:0] sp_inst_2_dout_w;
|
||||
wire [0:0] sp_inst_2_dout;
|
||||
wire [30:0] sp_inst_3_dout_w;
|
||||
wire [0:0] sp_inst_3_dout;
|
||||
wire [30:0] sp_inst_4_dout_w;
|
||||
wire [1:1] sp_inst_4_dout;
|
||||
wire [30:0] sp_inst_5_dout_w;
|
||||
wire [1:1] sp_inst_5_dout;
|
||||
wire [30:0] sp_inst_6_dout_w;
|
||||
wire [1:1] sp_inst_6_dout;
|
||||
wire [30:0] sp_inst_7_dout_w;
|
||||
wire [1:1] sp_inst_7_dout;
|
||||
wire [30:0] sp_inst_8_dout_w;
|
||||
wire [2:2] sp_inst_8_dout;
|
||||
wire [30:0] sp_inst_9_dout_w;
|
||||
wire [2:2] sp_inst_9_dout;
|
||||
wire [30:0] sp_inst_10_dout_w;
|
||||
wire [2:2] sp_inst_10_dout;
|
||||
wire [30:0] sp_inst_11_dout_w;
|
||||
wire [2:2] sp_inst_11_dout;
|
||||
wire [30:0] sp_inst_12_dout_w;
|
||||
wire [3:3] sp_inst_12_dout;
|
||||
wire [30:0] sp_inst_13_dout_w;
|
||||
wire [3:3] sp_inst_13_dout;
|
||||
wire [30:0] sp_inst_14_dout_w;
|
||||
wire [3:3] sp_inst_14_dout;
|
||||
wire [30:0] sp_inst_15_dout_w;
|
||||
wire [3:3] sp_inst_15_dout;
|
||||
wire [30:0] sp_inst_16_dout_w;
|
||||
wire [4:4] sp_inst_16_dout;
|
||||
wire [30:0] sp_inst_17_dout_w;
|
||||
wire [4:4] sp_inst_17_dout;
|
||||
wire [30:0] sp_inst_18_dout_w;
|
||||
wire [4:4] sp_inst_18_dout;
|
||||
wire [30:0] sp_inst_19_dout_w;
|
||||
wire [4:4] sp_inst_19_dout;
|
||||
wire [30:0] sp_inst_20_dout_w;
|
||||
wire [5:5] sp_inst_20_dout;
|
||||
wire [30:0] sp_inst_21_dout_w;
|
||||
wire [5:5] sp_inst_21_dout;
|
||||
wire [30:0] sp_inst_22_dout_w;
|
||||
wire [5:5] sp_inst_22_dout;
|
||||
wire [30:0] sp_inst_23_dout_w;
|
||||
wire [5:5] sp_inst_23_dout;
|
||||
wire [30:0] sp_inst_24_dout_w;
|
||||
wire [6:6] sp_inst_24_dout;
|
||||
wire [30:0] sp_inst_25_dout_w;
|
||||
wire [6:6] sp_inst_25_dout;
|
||||
wire [30:0] sp_inst_26_dout_w;
|
||||
wire [6:6] sp_inst_26_dout;
|
||||
wire [30:0] sp_inst_27_dout_w;
|
||||
wire [6:6] sp_inst_27_dout;
|
||||
wire [30:0] sp_inst_28_dout_w;
|
||||
wire [7:7] sp_inst_28_dout;
|
||||
wire [30:0] sp_inst_29_dout_w;
|
||||
wire [7:7] sp_inst_29_dout;
|
||||
wire [30:0] sp_inst_30_dout_w;
|
||||
wire [7:7] sp_inst_30_dout;
|
||||
wire [30:0] sp_inst_31_dout_w;
|
||||
wire [7:7] sp_inst_31_dout;
|
||||
wire dff_q_0;
|
||||
wire dff_q_1;
|
||||
wire mux_o_0;
|
||||
wire mux_o_1;
|
||||
wire mux_o_3;
|
||||
wire mux_o_4;
|
||||
wire mux_o_6;
|
||||
wire mux_o_7;
|
||||
wire mux_o_9;
|
||||
wire mux_o_10;
|
||||
wire mux_o_12;
|
||||
wire mux_o_13;
|
||||
wire mux_o_15;
|
||||
wire mux_o_16;
|
||||
wire mux_o_18;
|
||||
wire mux_o_19;
|
||||
wire mux_o_21;
|
||||
wire mux_o_22;
|
||||
wire ce_w;
|
||||
wire gw_gnd;
|
||||
|
||||
assign ce_w = ~wre & ce;
|
||||
assign gw_gnd = 1'b0;
|
||||
|
||||
SP sp_inst_0 (
|
||||
.DO({sp_inst_0_dout_w[30:0],sp_inst_0_dout[0]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[0]})
|
||||
);
|
||||
|
||||
defparam sp_inst_0.READ_MODE = 1'b0;
|
||||
defparam sp_inst_0.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_0.BIT_WIDTH = 1;
|
||||
defparam sp_inst_0.BLK_SEL = 3'b000;
|
||||
defparam sp_inst_0.RESET_MODE = "SYNC";
|
||||
defparam sp_inst_0.INIT_RAM_00 = 256'h000000000000000000000000000000000000000000000000000000000000038C;
|
||||
|
||||
SP sp_inst_1 (
|
||||
.DO({sp_inst_1_dout_w[30:0],sp_inst_1_dout[0]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[0]})
|
||||
);
|
||||
|
||||
defparam sp_inst_1.READ_MODE = 1'b0;
|
||||
defparam sp_inst_1.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_1.BIT_WIDTH = 1;
|
||||
defparam sp_inst_1.BLK_SEL = 3'b001;
|
||||
defparam sp_inst_1.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_2 (
|
||||
.DO({sp_inst_2_dout_w[30:0],sp_inst_2_dout[0]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[0]})
|
||||
);
|
||||
|
||||
defparam sp_inst_2.READ_MODE = 1'b0;
|
||||
defparam sp_inst_2.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_2.BIT_WIDTH = 1;
|
||||
defparam sp_inst_2.BLK_SEL = 3'b010;
|
||||
defparam sp_inst_2.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_3 (
|
||||
.DO({sp_inst_3_dout_w[30:0],sp_inst_3_dout[0]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[0]})
|
||||
);
|
||||
|
||||
defparam sp_inst_3.READ_MODE = 1'b0;
|
||||
defparam sp_inst_3.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_3.BIT_WIDTH = 1;
|
||||
defparam sp_inst_3.BLK_SEL = 3'b011;
|
||||
defparam sp_inst_3.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_4 (
|
||||
.DO({sp_inst_4_dout_w[30:0],sp_inst_4_dout[1]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[1]})
|
||||
);
|
||||
|
||||
defparam sp_inst_4.READ_MODE = 1'b0;
|
||||
defparam sp_inst_4.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_4.BIT_WIDTH = 1;
|
||||
defparam sp_inst_4.BLK_SEL = 3'b000;
|
||||
defparam sp_inst_4.RESET_MODE = "SYNC";
|
||||
defparam sp_inst_4.INIT_RAM_00 = 256'h00000000000000000000000000000000000000000000000000000000000004E8;
|
||||
|
||||
SP sp_inst_5 (
|
||||
.DO({sp_inst_5_dout_w[30:0],sp_inst_5_dout[1]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[1]})
|
||||
);
|
||||
|
||||
defparam sp_inst_5.READ_MODE = 1'b0;
|
||||
defparam sp_inst_5.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_5.BIT_WIDTH = 1;
|
||||
defparam sp_inst_5.BLK_SEL = 3'b001;
|
||||
defparam sp_inst_5.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_6 (
|
||||
.DO({sp_inst_6_dout_w[30:0],sp_inst_6_dout[1]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[1]})
|
||||
);
|
||||
|
||||
defparam sp_inst_6.READ_MODE = 1'b0;
|
||||
defparam sp_inst_6.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_6.BIT_WIDTH = 1;
|
||||
defparam sp_inst_6.BLK_SEL = 3'b010;
|
||||
defparam sp_inst_6.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_7 (
|
||||
.DO({sp_inst_7_dout_w[30:0],sp_inst_7_dout[1]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[1]})
|
||||
);
|
||||
|
||||
defparam sp_inst_7.READ_MODE = 1'b0;
|
||||
defparam sp_inst_7.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_7.BIT_WIDTH = 1;
|
||||
defparam sp_inst_7.BLK_SEL = 3'b011;
|
||||
defparam sp_inst_7.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_8 (
|
||||
.DO({sp_inst_8_dout_w[30:0],sp_inst_8_dout[2]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[2]})
|
||||
);
|
||||
|
||||
defparam sp_inst_8.READ_MODE = 1'b0;
|
||||
defparam sp_inst_8.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_8.BIT_WIDTH = 1;
|
||||
defparam sp_inst_8.BLK_SEL = 3'b000;
|
||||
defparam sp_inst_8.RESET_MODE = "SYNC";
|
||||
defparam sp_inst_8.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000040;
|
||||
|
||||
SP sp_inst_9 (
|
||||
.DO({sp_inst_9_dout_w[30:0],sp_inst_9_dout[2]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[2]})
|
||||
);
|
||||
|
||||
defparam sp_inst_9.READ_MODE = 1'b0;
|
||||
defparam sp_inst_9.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_9.BIT_WIDTH = 1;
|
||||
defparam sp_inst_9.BLK_SEL = 3'b001;
|
||||
defparam sp_inst_9.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_10 (
|
||||
.DO({sp_inst_10_dout_w[30:0],sp_inst_10_dout[2]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[2]})
|
||||
);
|
||||
|
||||
defparam sp_inst_10.READ_MODE = 1'b0;
|
||||
defparam sp_inst_10.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_10.BIT_WIDTH = 1;
|
||||
defparam sp_inst_10.BLK_SEL = 3'b010;
|
||||
defparam sp_inst_10.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_11 (
|
||||
.DO({sp_inst_11_dout_w[30:0],sp_inst_11_dout[2]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[2]})
|
||||
);
|
||||
|
||||
defparam sp_inst_11.READ_MODE = 1'b0;
|
||||
defparam sp_inst_11.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_11.BIT_WIDTH = 1;
|
||||
defparam sp_inst_11.BLK_SEL = 3'b011;
|
||||
defparam sp_inst_11.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_12 (
|
||||
.DO({sp_inst_12_dout_w[30:0],sp_inst_12_dout[3]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[3]})
|
||||
);
|
||||
|
||||
defparam sp_inst_12.READ_MODE = 1'b0;
|
||||
defparam sp_inst_12.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_12.BIT_WIDTH = 1;
|
||||
defparam sp_inst_12.BLK_SEL = 3'b000;
|
||||
defparam sp_inst_12.RESET_MODE = "SYNC";
|
||||
defparam sp_inst_12.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000012;
|
||||
|
||||
SP sp_inst_13 (
|
||||
.DO({sp_inst_13_dout_w[30:0],sp_inst_13_dout[3]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[3]})
|
||||
);
|
||||
|
||||
defparam sp_inst_13.READ_MODE = 1'b0;
|
||||
defparam sp_inst_13.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_13.BIT_WIDTH = 1;
|
||||
defparam sp_inst_13.BLK_SEL = 3'b001;
|
||||
defparam sp_inst_13.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_14 (
|
||||
.DO({sp_inst_14_dout_w[30:0],sp_inst_14_dout[3]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[3]})
|
||||
);
|
||||
|
||||
defparam sp_inst_14.READ_MODE = 1'b0;
|
||||
defparam sp_inst_14.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_14.BIT_WIDTH = 1;
|
||||
defparam sp_inst_14.BLK_SEL = 3'b010;
|
||||
defparam sp_inst_14.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_15 (
|
||||
.DO({sp_inst_15_dout_w[30:0],sp_inst_15_dout[3]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[3]})
|
||||
);
|
||||
|
||||
defparam sp_inst_15.READ_MODE = 1'b0;
|
||||
defparam sp_inst_15.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_15.BIT_WIDTH = 1;
|
||||
defparam sp_inst_15.BLK_SEL = 3'b011;
|
||||
defparam sp_inst_15.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_16 (
|
||||
.DO({sp_inst_16_dout_w[30:0],sp_inst_16_dout[4]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[4]})
|
||||
);
|
||||
|
||||
defparam sp_inst_16.READ_MODE = 1'b0;
|
||||
defparam sp_inst_16.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_16.BIT_WIDTH = 1;
|
||||
defparam sp_inst_16.BLK_SEL = 3'b000;
|
||||
defparam sp_inst_16.RESET_MODE = "SYNC";
|
||||
defparam sp_inst_16.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
SP sp_inst_17 (
|
||||
.DO({sp_inst_17_dout_w[30:0],sp_inst_17_dout[4]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[4]})
|
||||
);
|
||||
|
||||
defparam sp_inst_17.READ_MODE = 1'b0;
|
||||
defparam sp_inst_17.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_17.BIT_WIDTH = 1;
|
||||
defparam sp_inst_17.BLK_SEL = 3'b001;
|
||||
defparam sp_inst_17.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_18 (
|
||||
.DO({sp_inst_18_dout_w[30:0],sp_inst_18_dout[4]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[4]})
|
||||
);
|
||||
|
||||
defparam sp_inst_18.READ_MODE = 1'b0;
|
||||
defparam sp_inst_18.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_18.BIT_WIDTH = 1;
|
||||
defparam sp_inst_18.BLK_SEL = 3'b010;
|
||||
defparam sp_inst_18.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_19 (
|
||||
.DO({sp_inst_19_dout_w[30:0],sp_inst_19_dout[4]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[4]})
|
||||
);
|
||||
|
||||
defparam sp_inst_19.READ_MODE = 1'b0;
|
||||
defparam sp_inst_19.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_19.BIT_WIDTH = 1;
|
||||
defparam sp_inst_19.BLK_SEL = 3'b011;
|
||||
defparam sp_inst_19.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_20 (
|
||||
.DO({sp_inst_20_dout_w[30:0],sp_inst_20_dout[5]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[5]})
|
||||
);
|
||||
|
||||
defparam sp_inst_20.READ_MODE = 1'b0;
|
||||
defparam sp_inst_20.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_20.BIT_WIDTH = 1;
|
||||
defparam sp_inst_20.BLK_SEL = 3'b000;
|
||||
defparam sp_inst_20.RESET_MODE = "SYNC";
|
||||
defparam sp_inst_20.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000008;
|
||||
|
||||
SP sp_inst_21 (
|
||||
.DO({sp_inst_21_dout_w[30:0],sp_inst_21_dout[5]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[5]})
|
||||
);
|
||||
|
||||
defparam sp_inst_21.READ_MODE = 1'b0;
|
||||
defparam sp_inst_21.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_21.BIT_WIDTH = 1;
|
||||
defparam sp_inst_21.BLK_SEL = 3'b001;
|
||||
defparam sp_inst_21.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_22 (
|
||||
.DO({sp_inst_22_dout_w[30:0],sp_inst_22_dout[5]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[5]})
|
||||
);
|
||||
|
||||
defparam sp_inst_22.READ_MODE = 1'b0;
|
||||
defparam sp_inst_22.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_22.BIT_WIDTH = 1;
|
||||
defparam sp_inst_22.BLK_SEL = 3'b010;
|
||||
defparam sp_inst_22.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_23 (
|
||||
.DO({sp_inst_23_dout_w[30:0],sp_inst_23_dout[5]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[5]})
|
||||
);
|
||||
|
||||
defparam sp_inst_23.READ_MODE = 1'b0;
|
||||
defparam sp_inst_23.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_23.BIT_WIDTH = 1;
|
||||
defparam sp_inst_23.BLK_SEL = 3'b011;
|
||||
defparam sp_inst_23.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_24 (
|
||||
.DO({sp_inst_24_dout_w[30:0],sp_inst_24_dout[6]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[6]})
|
||||
);
|
||||
|
||||
defparam sp_inst_24.READ_MODE = 1'b0;
|
||||
defparam sp_inst_24.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_24.BIT_WIDTH = 1;
|
||||
defparam sp_inst_24.BLK_SEL = 3'b000;
|
||||
defparam sp_inst_24.RESET_MODE = "SYNC";
|
||||
defparam sp_inst_24.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000052;
|
||||
|
||||
SP sp_inst_25 (
|
||||
.DO({sp_inst_25_dout_w[30:0],sp_inst_25_dout[6]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[6]})
|
||||
);
|
||||
|
||||
defparam sp_inst_25.READ_MODE = 1'b0;
|
||||
defparam sp_inst_25.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_25.BIT_WIDTH = 1;
|
||||
defparam sp_inst_25.BLK_SEL = 3'b001;
|
||||
defparam sp_inst_25.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_26 (
|
||||
.DO({sp_inst_26_dout_w[30:0],sp_inst_26_dout[6]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[6]})
|
||||
);
|
||||
|
||||
defparam sp_inst_26.READ_MODE = 1'b0;
|
||||
defparam sp_inst_26.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_26.BIT_WIDTH = 1;
|
||||
defparam sp_inst_26.BLK_SEL = 3'b010;
|
||||
defparam sp_inst_26.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_27 (
|
||||
.DO({sp_inst_27_dout_w[30:0],sp_inst_27_dout[6]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[6]})
|
||||
);
|
||||
|
||||
defparam sp_inst_27.READ_MODE = 1'b0;
|
||||
defparam sp_inst_27.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_27.BIT_WIDTH = 1;
|
||||
defparam sp_inst_27.BLK_SEL = 3'b011;
|
||||
defparam sp_inst_27.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_28 (
|
||||
.DO({sp_inst_28_dout_w[30:0],sp_inst_28_dout[7]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7]})
|
||||
);
|
||||
|
||||
defparam sp_inst_28.READ_MODE = 1'b0;
|
||||
defparam sp_inst_28.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_28.BIT_WIDTH = 1;
|
||||
defparam sp_inst_28.BLK_SEL = 3'b000;
|
||||
defparam sp_inst_28.RESET_MODE = "SYNC";
|
||||
defparam sp_inst_28.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
||||
SP sp_inst_29 (
|
||||
.DO({sp_inst_29_dout_w[30:0],sp_inst_29_dout[7]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7]})
|
||||
);
|
||||
|
||||
defparam sp_inst_29.READ_MODE = 1'b0;
|
||||
defparam sp_inst_29.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_29.BIT_WIDTH = 1;
|
||||
defparam sp_inst_29.BLK_SEL = 3'b001;
|
||||
defparam sp_inst_29.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_30 (
|
||||
.DO({sp_inst_30_dout_w[30:0],sp_inst_30_dout[7]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7]})
|
||||
);
|
||||
|
||||
defparam sp_inst_30.READ_MODE = 1'b0;
|
||||
defparam sp_inst_30.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_30.BIT_WIDTH = 1;
|
||||
defparam sp_inst_30.BLK_SEL = 3'b010;
|
||||
defparam sp_inst_30.RESET_MODE = "SYNC";
|
||||
|
||||
SP sp_inst_31 (
|
||||
.DO({sp_inst_31_dout_w[30:0],sp_inst_31_dout[7]}),
|
||||
.CLK(clk),
|
||||
.OCE(oce),
|
||||
.CE(ce),
|
||||
.RESET(reset),
|
||||
.WRE(wre),
|
||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
||||
.AD(ad[13:0]),
|
||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7]})
|
||||
);
|
||||
|
||||
defparam sp_inst_31.READ_MODE = 1'b0;
|
||||
defparam sp_inst_31.WRITE_MODE = 2'b00;
|
||||
defparam sp_inst_31.BIT_WIDTH = 1;
|
||||
defparam sp_inst_31.BLK_SEL = 3'b011;
|
||||
defparam sp_inst_31.RESET_MODE = "SYNC";
|
||||
|
||||
DFFE dff_inst_0 (
|
||||
.Q(dff_q_0),
|
||||
.D(ad[15]),
|
||||
.CLK(clk),
|
||||
.CE(ce_w)
|
||||
);
|
||||
DFFE dff_inst_1 (
|
||||
.Q(dff_q_1),
|
||||
.D(ad[14]),
|
||||
.CLK(clk),
|
||||
.CE(ce_w)
|
||||
);
|
||||
MUX2 mux_inst_0 (
|
||||
.O(mux_o_0),
|
||||
.I0(sp_inst_0_dout[0]),
|
||||
.I1(sp_inst_1_dout[0]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_1 (
|
||||
.O(mux_o_1),
|
||||
.I0(sp_inst_2_dout[0]),
|
||||
.I1(sp_inst_3_dout[0]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_2 (
|
||||
.O(dout[0]),
|
||||
.I0(mux_o_0),
|
||||
.I1(mux_o_1),
|
||||
.S0(dff_q_0)
|
||||
);
|
||||
MUX2 mux_inst_3 (
|
||||
.O(mux_o_3),
|
||||
.I0(sp_inst_4_dout[1]),
|
||||
.I1(sp_inst_5_dout[1]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_4 (
|
||||
.O(mux_o_4),
|
||||
.I0(sp_inst_6_dout[1]),
|
||||
.I1(sp_inst_7_dout[1]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_5 (
|
||||
.O(dout[1]),
|
||||
.I0(mux_o_3),
|
||||
.I1(mux_o_4),
|
||||
.S0(dff_q_0)
|
||||
);
|
||||
MUX2 mux_inst_6 (
|
||||
.O(mux_o_6),
|
||||
.I0(sp_inst_8_dout[2]),
|
||||
.I1(sp_inst_9_dout[2]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_7 (
|
||||
.O(mux_o_7),
|
||||
.I0(sp_inst_10_dout[2]),
|
||||
.I1(sp_inst_11_dout[2]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_8 (
|
||||
.O(dout[2]),
|
||||
.I0(mux_o_6),
|
||||
.I1(mux_o_7),
|
||||
.S0(dff_q_0)
|
||||
);
|
||||
MUX2 mux_inst_9 (
|
||||
.O(mux_o_9),
|
||||
.I0(sp_inst_12_dout[3]),
|
||||
.I1(sp_inst_13_dout[3]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_10 (
|
||||
.O(mux_o_10),
|
||||
.I0(sp_inst_14_dout[3]),
|
||||
.I1(sp_inst_15_dout[3]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_11 (
|
||||
.O(dout[3]),
|
||||
.I0(mux_o_9),
|
||||
.I1(mux_o_10),
|
||||
.S0(dff_q_0)
|
||||
);
|
||||
MUX2 mux_inst_12 (
|
||||
.O(mux_o_12),
|
||||
.I0(sp_inst_16_dout[4]),
|
||||
.I1(sp_inst_17_dout[4]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_13 (
|
||||
.O(mux_o_13),
|
||||
.I0(sp_inst_18_dout[4]),
|
||||
.I1(sp_inst_19_dout[4]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_14 (
|
||||
.O(dout[4]),
|
||||
.I0(mux_o_12),
|
||||
.I1(mux_o_13),
|
||||
.S0(dff_q_0)
|
||||
);
|
||||
MUX2 mux_inst_15 (
|
||||
.O(mux_o_15),
|
||||
.I0(sp_inst_20_dout[5]),
|
||||
.I1(sp_inst_21_dout[5]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_16 (
|
||||
.O(mux_o_16),
|
||||
.I0(sp_inst_22_dout[5]),
|
||||
.I1(sp_inst_23_dout[5]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_17 (
|
||||
.O(dout[5]),
|
||||
.I0(mux_o_15),
|
||||
.I1(mux_o_16),
|
||||
.S0(dff_q_0)
|
||||
);
|
||||
MUX2 mux_inst_18 (
|
||||
.O(mux_o_18),
|
||||
.I0(sp_inst_24_dout[6]),
|
||||
.I1(sp_inst_25_dout[6]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_19 (
|
||||
.O(mux_o_19),
|
||||
.I0(sp_inst_26_dout[6]),
|
||||
.I1(sp_inst_27_dout[6]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_20 (
|
||||
.O(dout[6]),
|
||||
.I0(mux_o_18),
|
||||
.I1(mux_o_19),
|
||||
.S0(dff_q_0)
|
||||
);
|
||||
MUX2 mux_inst_21 (
|
||||
.O(mux_o_21),
|
||||
.I0(sp_inst_28_dout[7]),
|
||||
.I1(sp_inst_29_dout[7]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_22 (
|
||||
.O(mux_o_22),
|
||||
.I0(sp_inst_30_dout[7]),
|
||||
.I1(sp_inst_31_dout[7]),
|
||||
.S0(dff_q_1)
|
||||
);
|
||||
MUX2 mux_inst_23 (
|
||||
.O(dout[7]),
|
||||
.I0(mux_o_21),
|
||||
.I1(mux_o_22),
|
||||
.S0(dff_q_0)
|
||||
);
|
||||
endmodule //spMem
|
||||
24
src/gowin_sp/gowin_sp_tmp.v
Normal file
24
src/gowin_sp/gowin_sp_tmp.v
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
|
||||
//All rights reserved.
|
||||
//File Title: Template file for instantiation
|
||||
//GOWIN Version: V1.9.9 Beta-4 Education
|
||||
//Part Number: GW2AR-LV18QN88C8/I7
|
||||
//Device: GW2AR-18
|
||||
//Device Version: C
|
||||
//Created Time: Wed Nov 15 04:42:39 2023
|
||||
|
||||
//Change the instance name and port connections to the signal names
|
||||
//--------Copy here to design--------
|
||||
|
||||
spMem your_instance_name(
|
||||
.dout(dout_o), //output [7:0] dout
|
||||
.clk(clk_i), //input clk
|
||||
.oce(oce_i), //input oce
|
||||
.ce(ce_i), //input ce
|
||||
.reset(reset_i), //input reset
|
||||
.wre(wre_i), //input wre
|
||||
.ad(ad_i), //input [15:0] ad
|
||||
.din(din_i) //input [7:0] din
|
||||
);
|
||||
|
||||
//--------Copy end-------------------
|
||||
13
src/holeybeepo.cst
Normal file
13
src/holeybeepo.cst
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
|
||||
//All rights reserved.
|
||||
//File Title: Physical Constraints file
|
||||
//GOWIN Version: 1.9.9 Beta-4 Education
|
||||
//Part Number: GW2AR-LV18QN88C8/I7
|
||||
//Device: GW2AR-18
|
||||
//Device Version: C
|
||||
//Created Time: Tue 11 14 12:00:04 2023
|
||||
|
||||
IO_LOC "o_uart_tx" 69;
|
||||
IO_PORT "o_uart_tx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
|
||||
IO_LOC "i_clk" 4;
|
||||
IO_PORT "i_clk" PULL_MODE=UP BANK_VCCIO=1.8;
|
||||
32
src/instructions.v
Normal file
32
src/instructions.v
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
// Based on https://git.ablecorp.us/AbleOS/holey-bytes/src/branch/trunk/spec.md
|
||||
|
||||
// Program execution control
|
||||
`define UN 'h00
|
||||
`define UN_ARGS {ARG_N, ARG_N, ARG_N, ARG_N}
|
||||
|
||||
// Binary register-register operations
|
||||
`define ADD8 'h03
|
||||
`define ADD8_ARGS {ARG_R, ARG_R, ARG_R, ARG_N}
|
||||
|
||||
// Merged divide-remainder
|
||||
`define DIRU8 'h20
|
||||
|
||||
// Unary register operations
|
||||
`define NEG 'h28
|
||||
`define NOT 'h29
|
||||
|
||||
// Binary register-immediate operations
|
||||
`define ADDI8 'h2D
|
||||
|
||||
// Register-immediate bitshifts
|
||||
`define SLUI8 'h38
|
||||
|
||||
// Register copies
|
||||
`define CP 'h46
|
||||
|
||||
// Load immediate
|
||||
`define LI8 'h48
|
||||
`define LI8_ARGS {ARG_R, ARG_B, ARG_N, ARG_N}
|
||||
|
||||
// Conditional jump
|
||||
`define JEQ 'h56
|
||||
259
src/memory.mi
Normal file
259
src/memory.mi
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
#File_format=Bin
|
||||
#Address_depth=256
|
||||
#Data_width=8
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
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137
src/uart_tx.v
Normal file
137
src/uart_tx.v
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
// This file comes from https://github.com/sipeed/TangNano-20K-example/blob/d8e3cfb86ac19966244cc99d12c1da84d7ba4199/uart/src/uart_tx.v
|
||||
|
||||
module uart_tx
|
||||
#(
|
||||
parameter CLK_FRE = 50, //clock frequency(Mhz)
|
||||
parameter BAUD_RATE = 115200 //serial baud rate
|
||||
)
|
||||
(
|
||||
input clk, //clock input
|
||||
input rst_n, //asynchronous reset input, low active
|
||||
input[7:0] tx_data, //data to send
|
||||
input tx_data_valid, //data to be sent is valid
|
||||
output reg tx_data_ready, //send ready
|
||||
output tx_pin //serial data output
|
||||
);
|
||||
//calculates the clock cycle for baud rate
|
||||
localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
|
||||
//state machine code
|
||||
localparam S_IDLE = 1;
|
||||
localparam S_START = 2;//start bit
|
||||
localparam S_SEND_BYTE = 3;//data bits
|
||||
localparam S_STOP = 4;//stop bit
|
||||
reg[2:0] state;
|
||||
reg[2:0] next_state;
|
||||
reg[15:0] cycle_cnt; //baud counter
|
||||
reg[2:0] bit_cnt;//bit counter
|
||||
reg[7:0] tx_data_latch; //latch data to send
|
||||
reg tx_reg; //serial data output
|
||||
|
||||
assign tx_pin = tx_reg;
|
||||
|
||||
always@(posedge clk or negedge rst_n)
|
||||
begin
|
||||
if(rst_n == 1'b0)
|
||||
state <= S_IDLE;
|
||||
else
|
||||
state <= next_state;
|
||||
end
|
||||
|
||||
always@(*)
|
||||
begin
|
||||
case(state)
|
||||
S_IDLE:
|
||||
if(tx_data_valid == 1'b1)
|
||||
next_state <= S_START;
|
||||
else
|
||||
next_state <= S_IDLE;
|
||||
S_START:
|
||||
if(cycle_cnt == CYCLE - 1)
|
||||
next_state <= S_SEND_BYTE;
|
||||
else
|
||||
next_state <= S_START;
|
||||
S_SEND_BYTE:
|
||||
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
|
||||
next_state <= S_STOP;
|
||||
else
|
||||
next_state <= S_SEND_BYTE;
|
||||
S_STOP:
|
||||
if(cycle_cnt == CYCLE - 1)
|
||||
next_state <= S_IDLE;
|
||||
else
|
||||
next_state <= S_STOP;
|
||||
default:
|
||||
next_state <= S_IDLE;
|
||||
endcase
|
||||
end
|
||||
always@(posedge clk or negedge rst_n)
|
||||
begin
|
||||
if(rst_n == 1'b0)
|
||||
begin
|
||||
tx_data_ready <= 1'b0;
|
||||
end
|
||||
else if(state == S_IDLE)
|
||||
if(tx_data_valid == 1'b1)
|
||||
tx_data_ready <= 1'b0;
|
||||
else
|
||||
tx_data_ready <= 1'b1;
|
||||
else if(state == S_STOP && cycle_cnt == CYCLE - 1)
|
||||
tx_data_ready <= 1'b1;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge rst_n)
|
||||
begin
|
||||
if(rst_n == 1'b0)
|
||||
begin
|
||||
tx_data_latch <= 8'd0;
|
||||
end
|
||||
else if(state == S_IDLE && tx_data_valid == 1'b1)
|
||||
tx_data_latch <= tx_data;
|
||||
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rst_n)
|
||||
begin
|
||||
if(rst_n == 1'b0)
|
||||
begin
|
||||
bit_cnt <= 3'd0;
|
||||
end
|
||||
else if(state == S_SEND_BYTE)
|
||||
if(cycle_cnt == CYCLE - 1)
|
||||
bit_cnt <= bit_cnt + 3'd1;
|
||||
else
|
||||
bit_cnt <= bit_cnt;
|
||||
else
|
||||
bit_cnt <= 3'd0;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge rst_n)
|
||||
begin
|
||||
if(rst_n == 1'b0)
|
||||
cycle_cnt <= 16'd0;
|
||||
else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
|
||||
cycle_cnt <= 16'd0;
|
||||
else
|
||||
cycle_cnt <= cycle_cnt + 16'd1;
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rst_n)
|
||||
begin
|
||||
if(rst_n == 1'b0)
|
||||
tx_reg <= 1'b1;
|
||||
else
|
||||
case(state)
|
||||
S_IDLE,S_STOP:
|
||||
tx_reg <= 1'b1;
|
||||
S_START:
|
||||
tx_reg <= 1'b0;
|
||||
S_SEND_BYTE:
|
||||
tx_reg <= tx_data_latch[bit_cnt];
|
||||
default:
|
||||
tx_reg <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
11
tests/Makefile
Normal file
11
tests/Makefile
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
ICARUS_FILES = inputs.txt
|
||||
ICARUS_OUT = out
|
||||
|
||||
build: ${ICARUS_FILES}
|
||||
iverilog -o ${ICARUS_OUT} -c $^ -s tb_beepo -g2005-sv
|
||||
|
||||
vvp: build
|
||||
vvp ${ICARUS_OUT}
|
||||
|
||||
wave: vvp
|
||||
gtkwave dump.vcd
|
||||
32
tests/beepo.v
Normal file
32
tests/beepo.v
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
`include "../src/beepo.v"
|
||||
`timescale 100us/10ns
|
||||
|
||||
module tb_beepo(
|
||||
output o_uart_tx
|
||||
);
|
||||
|
||||
reg clk = 0;
|
||||
|
||||
Beepo #(
|
||||
.FREQ(1)
|
||||
) bep (
|
||||
.i_clk(clk),
|
||||
.o_uart_tx(o_uart_tx)
|
||||
);
|
||||
|
||||
localparam CLK_PERIOD = 1.0;
|
||||
always #(CLK_PERIOD/2) clk=~clk;
|
||||
|
||||
initial begin
|
||||
$dumpfile("dump.vcd");
|
||||
$dumpvars(0, tb_beepo, bep.r_registers[1],
|
||||
bep.r_arg_types[0], bep.r_arg_types[1],
|
||||
bep.r_arg_types[2], bep.r_arg_types[3],
|
||||
bep.r_arg_regs[0], bep.r_arg_regs[1],
|
||||
bep.r_arg_regs[2], bep.r_arg_regs[3]
|
||||
);
|
||||
end
|
||||
|
||||
initial #10000 $finish;
|
||||
|
||||
endmodule
|
||||
4
tests/inputs.txt
Normal file
4
tests/inputs.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
../src/instructions.v
|
||||
beepo.v
|
||||
../src/uart_tx.v
|
||||
spmem.v
|
||||
20
tests/spmem.v
Normal file
20
tests/spmem.v
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
module spMem(
|
||||
output [7:0] dout,
|
||||
input clk,
|
||||
input oce,
|
||||
input ce,
|
||||
input reset,
|
||||
input wre,
|
||||
input [15:0] ad,
|
||||
input [7:0] din
|
||||
);
|
||||
reg [0:255] mem = {
|
||||
8'h0,
|
||||
8'h48, 8'h01, 8'h23,
|
||||
8'h48, 8'h02, 8'h46,
|
||||
8'h03, 8'h01, 8'h01, 8'h02,
|
||||
168'h0
|
||||
};
|
||||
|
||||
assign dout = mem[ad*8+:8];
|
||||
endmodule
|
||||
Loading…
Reference in a new issue