.gitignore

@@ -3,7 +3,4 @@ impl/
 tests/**/*.vcd
 tests/**/out
 src/gowin_*/
-**/target/
+**/target/
-**/build/
-tests/slapper
-tests/hbasm

src/beepo.v

@@ -210,7 +210,7 @@ module Beepo #(
         .ce(1'b1),     //input ce
         .reset(1'b0),  //input reset
         .wre(1'b0),    //input wre (write enable)
-        .ad(r_pc_latch[0+:32]),    //input [15:0] ad
+        .ad(r_pc_latch[31:0]),    //input [15:0] ad
         .din(1'b0)     //input [7:0] din
     );
 endmodule

tests/Makefile

@@ -0,0 +1,30 @@
+ICARUS_FILES = inputs.txt
+
+# Used in all tests
+build:
+	mkdir -p $@
+
+release/slapper:
+	cargo build --manifest-path ../slapper/Cargo.toml -r
+
+slapper: release/slapper
+	cp ../slapper/target/release/slapper $@
+
+# Addition tests
+build/adding: | build
+	mkdir -p $@
+
+build/adding/program.bin: adding/program.rhai | build/adding
+	./hbasm $< > $@
+
+build/adding/spmem_gen.v: build/adding/program.bin slapper | build/adding
+	./slapper $< spmem.v $@
+
+build/adding/out: ${ICARUS_FILES} build/adding/spmem_gen.v | build/adding
+	iverilog -o $@ -c $< -s tb_adding
+
+build/adding/dump.vcd: build/adding/out | build/adding
+	vvp $<
+
+adding-wave: build/adding/dump.vcd | build/adding
+	gtkwave build/adding/dump.vcd

tests/adding/Makefile

@@ -1,38 +0,0 @@
-SLAPPER_DIR		= ../../slapper
-SLAPPER_BUILD	= ${SLAPPER_DIR}/target/release/slapper
-SLAPPER		 	= ../slapper
-HBASM	 		= ../hbasm
-SPMEM			= ../spmem.v
-
-INPUT_FILE 	= inputs.txt
-BUILD_DEPS = ../../src/beepo.v ../../src/instructions.v adding.v ../../src/uart_tx.v ../../src/multi7.v build/spmem_gen.v
-
-
-${SLAPPER_BUILD}:
-	cargo build --manifest-path ${SLAPPER_DIR}/Cargo.toml -r
-
-${SLAPPER}: ${SLAPPER_BUILD}
-	cp $< $@
-
-build:
-	mkdir -p $@
-
-build/program.bin: program.rhai | build
-	${HBASM} $< > $@
-
-build/spmem_gen.v: build/program.bin ${SLAPPER}
-	${SLAPPER} $< ${SPMEM} $@
-
-build/out: ${INPUT_FILE} ${BUILD_DEPS} build/spmem_gen.v
-	iverilog -o $@ -c $< -s tb_adding
-
-build/dump.vcd: build/out
-	vvp $<
-
-wave: build/dump.vcd
-	gtkwave build/dump.vcd
-
-assemble: build/program.bin
-insert-mem: build/spmem_gen.v
-synthesize: build/out
-run: build/dump.vcd

tests/adding/adding.bin

@@ -0,0 +1 @@
+H
IJK








-

.

/

0



tests/adding/adding.v

@@ -21,14 +21,19 @@ module tb_adding();
     always #(CLK_PERIOD/2) clk=~clk;
 
     initial begin
-        $dumpfile("build/dump.vcd");
+        $dumpfile("dump.vcd");
-        $dumpvars(0, tb_adding, bep.r_registers[1]);
+        $dumpvars(0, tb_adding,
+            bep.r_registers[1], bep.r_registers[2],
+            bep.r_arg_types[0], bep.r_arg_types[1],
+            bep.r_arg_types[2], bep.r_arg_types[3],
+            bep.r_arg_regs[0], bep.r_arg_regs[1],
+            bep.r_arg_regs[2], bep.r_arg_regs[3]
+        );
     end
 
     // should probably do more granular tests
     initial #10000 begin
         `assert(bep.r_registers[1], 64'h2020202040406090);
-        $display("[ADDING] All tests passed");
         $finish;
     end
 endmodule

tests/adding/build/adding.bin

@@ -0,0 +1 @@
+H
IJK








-

.

/

0



tests/adding/build/spmem_gen.v

@@ -0,0 +1,24 @@
+module spMem(
+    output [7:0] dout,
+    input clk,
+    input oce,
+    input ce,
+    input reset,
+    input wre,
+    input [15:0] ad,
+    input [7:0] din
+);
+    // gets replaced with the memory for the program to run
+    reg [0:535] mem = 536'h480110490210104A03101010104B041010101010101010030101010401010205010103060101042D0101102E010110102F010110101010300101101010101010101001;
+
+    reg [15:0]  r_ad_prev = 0;
+    reg [7:0]   r_out;
+
+    assign dout = r_out;
+
+    always @(negedge clk) begin
+        // one full clock cycle before being fetched
+        if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
+        else r_ad_prev = ad;
+    end
+endmodule

tests/adding/mem.py

@@ -0,0 +1,7 @@
+with open("adding.bin", "rb") as f:
+    content = f.read()
+    length_bits = len(content) * 8
+    mash = "".join([hex(int(i))[2:].zfill(2) for i in content])
+    shadow = f"reg [0:{length_bits-1}] mem = {length_bits}'h{mash}; // generated"
+
+    print(shadow)

tests/build/adding/spmem_gen.v

@@ -0,0 +1,24 @@
+module spMem(
+    output [7:0] dout,
+    input clk,
+    input oce,
+    input ce,
+    input reset,
+    input wre,
+    input [15:0] ad,
+    input [7:0] din
+);
+    // gets replaced with the memory for the program to run
+    reg [0:18446744073709551615] mem = 0'h;
+
+    reg [15:0]  r_ad_prev = 0;
+    reg [7:0]   r_out;
+
+    assign dout = r_out;
+
+    always @(negedge clk) begin
+        // one full clock cycle before being fetched
+        if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
+        else r_ad_prev = ad;
+    end
+endmodule

tests/build/adding_mem.v

@@ -0,0 +1,24 @@
+module spMem(
+    output [7:0] dout,
+    input clk,
+    input oce,
+    input ce,
+    input reset,
+    input wre,
+    input [15:0] ad,
+    input [7:0] din
+);
+    // gets replaced with the memory for the program to run
+    reg [0:18446744073709551615] mem = 0'h;
+
+    reg [15:0]  r_ad_prev = 0;
+    reg [7:0]   r_out;
+
+    assign dout = r_out;
+
+    always @(negedge clk) begin
+        // one full clock cycle before being fetched
+        if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
+        else r_ad_prev = ad;
+    end
+endmodule

tests/inputs.txt

@@ -2,4 +2,4 @@
 adding.v
 ../../src/uart_tx.v
 ../../src/multi7.v
-build/spmem_gen.v
+../build/adding_mem.v